Solid-state imaging device

ABSTRACT

A photoelectric conversion device suitable for use as an element of a photodetector array includes a photodiode for generating a first signal charge in response to incident light, an output unit including a JFET, and at least one transistor having an electrode that generates a second signal charge in response to incident light. The first and second signal charges may be output separately or combined. The second signal charge, or the first and second signal charges combined, may be monitored during an exposure time to determine the desired end of the exposure. An image sensor array may have one or more pixels with such light monitoring capability. The output signal for monitoring the light may be output over a reset drain interconnection, directly from the monitoring pixel or through other pixels via inter-pixel MOSFETS. Exposure time may be controlled, by timing a shutter or a strobe or the like, based on the monitored accumulation of signal charge during exposure. Microlenses may be provided on-chip to increase the effective aperture ratio of the array. The microlenses are designed to avoid interfering with the incident light used for monitoring. Resulting pixel-to-pixel variations in effective aperture ratio, if any, may be electronically compensated.

This application is a continuation-in-part of U.S. patent applicationSer. No. 09/152,138, filed Sep. 10, 1998.

FIELD OF THE INVENTION

The present invention relates to solid-state imaging devices andphotoelectric conversion devices used therein, particularly to imagecapturing apparatus and image sensor arrays useful in such apparatus forcapturing fixed images as in digital photography and the like.

BACKGROUND OF THE INVENTION

Photoelectric conversion devices using photodiodes as photoelectricconversion elements for generating signal charges corresponding toincident light are known in the art. An example of such a photoelectricconversion device is disclosed in, for example, Japanese Laid-OpenPatent Application No. 8-293591, which is the subject of U.S. patentapplication Ser. No. 08/606,995, assigned to the assignee of the presentapplication.

FIGS. 49, 50, and 51 of the present application show the structure of aphotoelectric conversion device as disclosed in Japanese Laid-OpenPatent Application No. 8-293591. FIG. 49 is a plan view of aphotoelectric conversion device 110, FIG. 50 is a cross-sectional viewtaken along the line X--X shown in FIG. 49, and FIG. 51 is across-sectional view taken along the line Y--Y shown in FIG. 49.

As shown in FIGS. 49-51, the photoelectric conversion device 110comprises as basic elements a photodiode 111 for generating andaccumulating a charge corresponding to the incident light; a junctionfield-effect transistor (JFET) 112 for outputting an electric signalVout corresponding to the signal charge received by its gate region112A; a transfer transistor 113 for supplying (or transferring) thesignal charge generated by and accumulated in the photodiode 111 to thegate region 112A of the JFET 112; and a reset transistor 114 forremoving the signal charge supplied to the gate region 112A of the JFET112.

FIG. 52 is a circuit diagram including the photoelectric conversiondevice 110 shown in FIG. 51 and a signal detection circuit 1190connected to the photoelectric conversion device 110. FIG. 53 is atiming chart showing the waveforms of a driving pulse TG supplied to thetransfer transistor QTG (113), a driving pulse φRSG supplied to a gate114C of the reset transistor QRSG (114), and a driving pulse φRSDsupplied to a reset drain 114B of the reset transistor QRSG (114),together with the waveform of the electric signal Vout occurring at thesource (node N1) of the JFET 112.

For the sake of convenience, the operation of the photoelectricconversion device 110 will be described beginning from the point in timet10. The driving pulse φRSG changes from a high level to a low level att10, which causes the reset transistor QRSG to be turned on. While thereset transistor QRSG is turned on, the driving pulse φRSD reaches areadout level (a constant voltage VGH), and this constant voltage VGH isapplied to the gate region 112A of the JFET 112 via the drain of thereset transistor QRSG.

The electric signal Vout occurring at the node N1 then becomes thereference signal voltage VD, which corresponds to a dark output.

At t11, the driving pulse φRSG becomes high, which causes the resettransistor QRSG to be turned off, and the voltage of driving pulse φRSDbecomes a low level (VGL). At this time, although the gate region 112Aof the JFET 112 is now in a floating state, the level of the electricsignal Vout occurring at the node N1 remains at VD.

At t12, the driving pulse φRSG returns to the low level again, and thereset transistor QRSG is turned on. Also at t12, the driving pulse φRSDreturns to the readout level (the constant voltage VGH), and thisconstant voltage VGH is applied to the gate region 112A of the JFET 112via the drain of the reset transistor QRSG.

At t13, the driving pulse φRSG becomes high, which causes the resettransistor QRSG to be turned off, putting the gate region 112A of theJFET 112 in a floating state.

At t14, the driving pulse φTG becomes low, turning on the transfertransistor QTG, whereby the signal charge generated and accumulated inthe photodiode 111 corresponding to the incident light is supplied tothe gate region 112A of the JFET 112. When the JFET 112 receives thesignal charge from the photodiode 111, the source voltage Vout (that is,the electric signal Vout occurring at the node N1) becomes a signalvoltage Vs corresponding to the signal charge supplied to the gateregion 112A, which signal charge corresponds to the incident light.

At t15, the driving pulse φTG is inverted to the high level, and thephotodiode 111 begins again generating and accumulating a signal charge.

At t20, the driving pulse φRSD becomes high and the driving pulse φRSGbecomes low and, then, the electric signal Vout occurring at the node N1becomes the reference signal voltage VD, which corresponds to the darkoutput.

The two electric signals VD and Vs occurring at the node N1 at differentpoints in time are output to the signal detection circuit shown in FIG.52. One of these two signal values (for example, VD) is stored and heldin a sample-and-hold circuit 1191, and a difference calculation circuit1192 subtracts this stored value VD from the other electric signal Vs,and outputs a photosignal Vp which does not contain the dark outputcomponent VD.

By removing the noise component VD (which results from, for example,fluctuation) from the electric signal Vs in the signal detection circuit1190, a photosignal Vp is obtained, whereby the photoelectric conversiondevice 110 can detect the incident light with high accuracy.

In order to block light, the semiconductor area of the photoelectricconversion device 110, except for the photodiode 111, is covered with areset drain interconnection (i.e., an aluminum interconnection) 1148(indicated by the region of wide-spaced diagonal top-left tobottom-right hatching in FIG. 49) which is connected to the drain of thereset transistor QRSG.

Other features of the photoelectric conversion device 110 are describedin more detail in the detailed description below. These include a P-typesemiconductor substrate 1101, an N-type layer 1102, an N⁺ -type layer1103, an insulating layer 1109, a P-type impurity diffusion layer 1121,a vertical signal line 1128, a transfer gate interconnection 1138, areset gate interconnection 1147, and a transfer gate 113C. Thesefeatures correspond to features in the example embodiments of theinvention with similar reference characters (reference charactersidentical except for the second digit). The functions of, andrelationships between, these features are the same as those describedfor corresponding features in the example embodiments of the inventionbelow.

FIG. 54 shows a single pixel of a fixed-image image sensor array inwhich a known photoelectric conversion element similar to that of FIG.49 is designed and structured for use as a pixel in a two-dimensionalarray of like pixels. FIG. 54(a) is a plan view, FIG. 54(b) is across-sectional view taken along the line X19-X20 in FIG. 54(a), andFIG. 54(c) is a cross-sectional view taken along the line Y19-Y20 inFIG. 54(a).

The structure of the pixel of FIG. 54 is formed on a P-typesemiconductor substrate 10 upon which an N-type semiconductor layer 11is formed. A photodiode 1 functions to accumulate charge in response toincident light. A transfer gate 3 functions as part of a transfertransistor to transfer accumulated charge from the photodiode 1 to anamplification transistor in the form of a JFET 2, specifically, to agate area 15 of the JFET 2. A reset gate 5 functions as part of a resettransistor in the form of a P-channel MOSFET 9, positioned to selectablyelectrically connect the gate area 15 with a reset drain 4. The resetgate 5, together with the gate area 15 and the reset drain 4 as majorelectrodes, forms the P-channel MOSFET 9.

The photodiode 1 comprises a P-type diffusion region 12 with ahigh-density N⁺ -type region 13 overlying the region 12. The JFET 2comprises a P-type gate region 15 sandwiching an N-type channel region17, and a high-density N⁺ -type source region 14. High-density N⁺ -typediffusion regions serve as pixel isolation regions 16 and as a drainregion for JFET 2.

A vertical signal line 22 connects the source regions 14 of JFETs 2 inone column of the array. Drain interconnect 25, through drain contactholes 32, provides a low-resistance conduction path for removing chargesfrom and controlling the potential of the drain and pixelisolation/drain region 16. Transfer gate interconnect 20 controls thetransfer gates 3 in one row of the array. Similarly, reset gateinterconnect 21 controls the reset gates 5 in one row of the array.Reset drain interconnect 24, via contact 31, relay 23, and relay contact30, controls the potential of the reset drains 4 in one row of thearray. Reset drain interconnect 24 also functions as a light shield overJFET 2 and reset drain 4, shielding them from exposure to incomingradiation, while leaving photodiode 1 exposed. An insulating dielectriclayer 33 supports and isolates the various interconnections and signallines.

FIG. 55 is a circuit diagram showing an existing fixed image captureapparatus with the single pixels shown in FIG. 54 arranged in atwo-dimensional matrix (m×n). The area of FIG. 55 surrounded by thedashed line is the single pixel equivalent circuit.

Each JFET 2 source area 14 (indicated by "S" in FIG. 55), is connectedmutually in each matrix column by vertical signal lines 22-1 through22-n (corresponding to vertical signal line 22 in FIG. 54).

Each JFET 2 drain area 16 (D) is connected to drain power source VDD,which is shared for all pixels, via a diffusion layer formedcontinuously along all the seams of the web that constitutes thepreviously discussed N-type drain area 16 and via the drain interconnect25.

Transfer gate 3 is connected in common in the horizontal scan directionto each row of the matrix by transfer gate interconnects 20-1 through20-m (corresponding to transfer gate interconnect 20 in FIG. 54) and isconnected to vertical scan circuit 7. In addition, each row is driven bydrive pulses φTG1 through φTGm provided from vertical scan circuit 7.

Reset gate 5 is connected in common to each row of the matrix in thehorizontal scan direction by reset gate interconnects 21-1 through 21-m(corresponding to reset gate interconnect 21 in FIG. 54), and isconnected to vertical scan circuit 7. In addition, each row is driven bydrive pulses φRSG1 through φRSGm provided from vertical scan circuit 7.

Reset drain 4 is connected in common to each matrix row in thehorizontal scan direction (row direction) by reset drain interconnects24-1 through 24-m (corresponding to reset drain interconnect 24 in FIG.54), and is connected to vertical scan circuit 7. In addition, each rowis driven by drive pulses (drive signals to discharge the charge fromJFET2 gate area 15 and to control the potential of said gate area 15)φRSD1 through φRSDm sent from vertical scan circuit 7.

Vertical signal lines 22-1 through 22-n are connected on one hand toconstant current sources 26-1 through 26-n. This permits constantcurrent to flow from constant current sources 26-1 through 26-n, therebyforming a source-follower circuit between JFET4 and constant currentsources 26-1 through 26-n. The output side of these source-followercircuits (the opposite end of the vertical signal lines 22-1 through22-n) are connected to sort-processing circuits 27-1 through 27-n, whichserve respectively as read circuits. Sort-processing circuits 27-1through 27-n comprise capacitors 28-1 through 28-n and MOSFET switches29-1 through 29-n. The gates of switches 29-1 through 29-n are connectedin common so as to be activated by pulse φN. The outputs ofsort-processing circuits 27-1 through 27-n are connected tosignal-output line 34 via horizontal-select switches 39-1 through 39-n.Horizontal-select switches 39-1 through 39-n are activated in sequenceby pulses φH1 through φHn sent from horizontal scan circuit 8, and theoutput from the sort processing circuits 27-1 through 27-n is output insequence to signal the output line 34. This output is fed by output line34 to output amp 35 for amplification and final output. Output signalline 34 is grounded (reset) by switch 36. The switch 36 is activated bya pulse φRH.

With the continuing improvement of semiconductor design and fabricationtechnologies, the number of pixels in image sensor arrays has increasedas pixel size has decreased, but the ratio of light-sensitive surfacearea to total light-receiving surface area, or aperture ratio, hastended to decline.

To improve the effective aperture ratio of image sensor arrays, on-chipmicrolenses have been developed. The microlenses collect and focus ontoa photosensitive element light from an area larger than thephotosensitive element itself. This increases the effective apertureratio, or the proportion of the image area that is sensitive to light.

Microlens technology has been described in Japanese Patent H9-64325, forexample. In the type of fixed-image image sensor array describedtherein, the area outside a photodiode that serves as a photoelectricconversion element is shielded by a shielding film formed on the array.Only information related to the light entering the photoelectricconversion element during the specified exposure time interval is outputoutside the array.

FIG. 56 illustrates part of the structure of a fixed-image imageCCD-type sensor array equipped with microlenses of this known type. FIG.56(a) is a plan view of the surface, while FIG. 56(b) is across-sectional view taken along the line A-A' in FIG. 56(a). Thestructure shown in FIG. 56 comprises a vertical electrode 2401, aphotodiode 2402, a microlens 2403, an Al (aluminum) light-shielding film2404, a photodiode N-type semiconductor area 2405, a photodiode P-typesemiconductor area 2406, a vertical N-type semiconductor area 2407, anda vertical P-type semiconductor area 2408. The area 2400 indicated bythe dashed line in FIG. 56(a) corresponds to a single pixel.

Light entering from the outside is focused onto the photodiode 2402 bythe microlens 2403, which, in effect, increases the aperture ratio, theratio of the light-sensitive surface area to total surface area.

Fixed-image image sensor arrays are typically exposed to a given imagefor a predetermined exposure interval. But whenever there is a suddenchange during the exposure interval in the amount of incoming light, itbecomes impossible to read out image information with optimal exposure.Generally this is dealt with by including a mechanical shutter apartfrom the fixed-image image sensor array, with the quantity of incominglight adjusted by controlling the open-close timing of the shutter. Anexposure control sensor capable of monitoring changes in incoming lightvolume during exposure is typically included. Such a sensor does notmonitor the response of the image-sensing array to the incoming light,but rather monitors the incoming light separately from thephotosensitive elements of which the image sensor array is comprised.

One goal in the design of a photoelectric conversion apparatus is toimprove the exposure control so that optimal exposure is a achieved evenwhen light levels fluctuate significantly during the exposure time.

Another goal in the design of a photoelectric conversion apparatus is toincrease the light-receiving area (e.g., the size of the photodiode 111)in each pixel (i.e., in each photoelectric conversion device 110), andto increase the effective light-receiving area.

In the conventional photoelectric conversion device 110, the signalcharge generated by the photodiode 111 according to the incident lightis amplified by the transistor 112 to generate an electric signal Vout.In order to provide for the amplification function, the transistor 112and the reset transistor 114 are included, in addition to the photodiode111, in each pixel (i.e., in each individual photoelectric conversiondevice). Since the amplification transistor 112 and the reset transistor114 require a certain amount of space, this limits the maximum size ofthe photodiode 111 within a pixel.

A third goal in the design of photoelectric conversion devices is toobtain a sufficient amount of the spectral characteristics (i.e., colorinformation) of the incident light when detecting the light using aphotoelectric conversion apparatus.

A known example of the use of a photoelectric conversion apparatus is inphotometry, which is a method for measuring the properties of an objectby emitting light having a specific wavelength toward the object andthen detecting the light radiated from that object.

For example, in order to perform photometry using blue light having aspecific wavelength, said blue light is emitted toward an object, andthe intensity of the light radiated from that object is detected. Thisradiation contains the blue light component and other light componentshaving wavelengths longer than that of the original blue light. Thespectral components of this radiation are detected and analyzed.However, the conventional photoelectric device can detect only a narrowrange of spectral components, using a color filter of a specific color.

OBJECTS AND SUMMARY OF THE INVENTION

It is an object of the present invention to overcome the problems in theprior art and to provide photoelectric conversion devices and imagesensor arrays comprised thereof and image capture apparatus employingsuch arrays, which allow a sharp image to be stably obtained despitechanges in the brightness of the surroundings. This is achieved byautomatically adjusting the exposure time in accordance with theenvironment in which the photoelectric conversion apparatus is placed.

It is another object of the invention to increase the light-receivingarea and/or effective light-receiving in each pixel in order to improvethe efficiency of the photoelectric conversion, and to allow a sharpphotosignal to be obtained with a low quantity of light.

It is still another object of the invention to provide photoelectricconversion devices and photoelectric conversion apparatus which canefficiently detect a wide range of wavelengths of incident lightaccording to its spectral components.

In order to achieve these objects, the present invention encompasses alight-receiving device, useful as a pixel element in a photodetectorarray. The device includes a light-receiving element that generates, inresponse to incident light, a first signal charge corresponding to theincident light. The light-receiving element is preferably a photodiode.The device further includes at least a first transistor structured andarranged such that at least a first electrode thereof itself generates,in response to incident light, a second signal charge corresponding tothe incident light.

The first and second signal charges may be combined (added together,summed) for output, or may be output individually from the device. Ifthe signal charges are added, the effective light gathering area and thecorresponding light gathering power of the device is increased. If thesignal charges are output or detected individually, the use of colorfilters allows increased spectral information to be detected by a singledevice. Color filters may also be used without separate output to allowdetection of--and/or exposure monitoring based on--specific wavelengths.

The accumulation of the second signal charge may be monitored duringexposure, so that a shutter may be closed after a desired exposure isreached. Alternatively, the first electrode of the first transistor maybe electrically connected to the light-receiving element duringexposure, so that the first and second signal charges are combined evenas they are generated, allowing direct monitoring of the entire signalcharge in order to control the exposure time.

The first transistor may be an amplification transistor having a controlelectrode (gate), and functioning in the device as part of an outputunit for providing an output signal corresponding to charge present atthe control electrode. The control electrode may be the first electrodeof the first transistor. The device may include a transfer unit,preferably in the form of a transfer transistor, for transferring thefirst signal charge to the control electrode. The transfer unit may besupplied with control signals so as to allow individual or combinedoutput and/or monitoring of the first and second signal charges.

The device may also include a second transistor structured and arrangedsuch that at least a first electrode thereof itself generates, inresponse to incident light, a third signal charge corresponding to theincident light. The first, second, and third signal charges may becombined all together or in a subcombination for output, or may beoutput individually. Combined output increases the light-gathering areaof the device. Separate output, with the use of color filters, allowsincreased detection of spectral content of the incident light. Thesecond and third signal charges may also be simultaneously monitoredduring exposure, with accumulation of either charge being able totrigger the end of the exposure upon reaching a respective predeterminedlevel.

The second transistor may be a reset transistor, and the first electrodeof the second transistor may be a drain electrode of the resettransistor. The device may include the provision of control signals tothe reset transistor such that the third signal charge, generated in thedrain electrode of the reset transistor, is output from via the drainelectrode of the reset transistor, either alone, or combined with thesecond signal charge. Alternatively, the third signal charge may beoutput via the control electrode of the amplification transistor, eitherseparately from or combined with both or either of the first and secondsignal charges.

Alternatively to the first transistor being an amplification transistor,the first transistor may be a reset transistor, and the first electrodemay be a drain electrode of the reset transistor. The device may theninclude the provision of control signals to the reset transistor suchthat the second signal charge, generated in the drain electrode of thereset transistor, is output separately from the first signal charge viathe drain electrode of the reset transistor, or is output via a controlelectrode of an amplification transistor, either separately from, orcombined with, the first signal charge.

The present invention also encompasses photoelectric conversionapparatus including one or more devices as described above, a shutter,and a shutter controller for controlling an exposure time based on themonitored accumulation of a signal charge in the one or more devices.

The present invention also includes photoelectric conversion apparatushaving an amplification transistor, the amplification transistor beingon only intermittently, rather than being constantly on, so as toconsume less power while still functioning to provide an output signalcorresponding to a charge present at its gate.

The present invention also includes image sensor arrays formed at leastin part of pixels comprising the inventive photoelectric conversiondevices. Specifically, the fixed-image image sensor array includes aregular array of pixels formed on the same silicon substrate, with atleast one pixel having both a first photosensitive surface and a secondphotosensitive surface, each surface being capable of providing anoutput signal, independent of the other's output. The image sensor arrayis typically a two-dimensional rectangular or square array, but may alsobe "one-dimensional" (i.e., rectangular with one-pixel width).

The image sensor array typically also includes pixels having only onephotosensitive area. Signals from pixels having only one such area andsignals from the first photosensitive area(s) of themulti-photosensitive-area pixel(s) are both read out in the normalfashion via an amplifier in the form of a JFET. Signals from the secondphotosensitive area(s) may also be read out via the JFET, but in themain embodiments are read out via reset drain interconnects. The secondphotosensitive area(s) can comprise at least a portion of the resetdrain of the associated first pixel.

The second photosensitive area(s) may be permanently electricallyconnected to the reset interconnection(s), or may be intermittently andselectably connected to the reset interconnection(s). Selectiveconnection may be accomplished via inter-pixel MOSFETs that connect asecond photosensitive area to an area (a JFET gate area) of an adjacentpixel, which is in turn connected, via one or more additional MOSFETs,to a reset drain connected to a reset drain interconnection.

The image sensor array may also be provided with a switch associatedwith each reset drain interconnect. The switch is so arranged as to beable to switch between to states: a first state in which a driving pulseis supplied to the reset drain interconnection and a second state inwhich an output signal may be read from the reset drain interconnection.

The image sensor array of the present invention may further be providedwith on-chip microlenses designed and structured particularly to allowfor use of the second photosensitive area.

Each first pixel of the array and each second pixel of the array mayhave a an on-chip microlens to focus incident light on the firstphotosensitive area of said first pixel and on the one and onlyphotosensitive area in the second pixel. The microlens on each type ofpixel may be identical or different, but in either case is shaped toavoid obscuring the second photosensitive area. If more than one type ofmicrolens is used in the array, the microlens on the firs pixel may besmaller than the others. A microlens on a second pixel adjacent thefirst pixel may also be smaller than the others to avoid obstructinglight incident to the second photosensitive area. The microlenses may behemispherical, cylindrical, or toric in shape. Identical microlenses maybe used on every pixel, with a hole cut in the lens material only overthe second photosensitive surface(s), or such holes may be made overevery pixel, regardless of any photosensitive surfaces underneath. Ineither case, the hole(s) may have sidewalls with a reflective layerpositioned thereon to inhibit cross-talk. In addition to any othermicrolenses, a microlens may be provided for the second photosensitivearea to increase the light gathering power of that surface, increasingthe low-light sensitivity of the exposure control process.

The image sensor array may be provided with an aperture ratiocompensator, particularly where different microlenses are used ondifferent pixels within the array. The compensator adjusts the signalsfrom the pixels so as to cancel differences in the signal levelsattributable to differing effective aperture ratios.

The invention also includes a fixed-image image capture apparatusincluding a light control device to control the exposure duration of animage sensor array based on the light incident during the exposure onthe second photosensitive surface(s). The light control device cancontrol the exposure duration by operating a shutter, or by operating astrobe light, to start and stop the exposure at the appropriate times.

More particular summary of various particular photoelectric conversiondevices of the present invention will now be given. Such devices areuseful as pixels in image sensor arrays.

In one aspect of the invention, a first respresentative embodiment of aphotoelectric conversion device comprises a photoelectric conversionelement for generating in response to incident light; a first signalcharge, corresponding to the incident light; an output unit comprisingan amplification transistor with a control electrode for outputting anelectric signal corresponding to charge present in the controlelectrode; a transfer unit for supplying the signal charge generated bythe photoelectric conversion element to the control electrode; and asignal line for supplying a control signal to the transfer unit.

As a feature of the device according to this aspect of the invention,the amplification transistor is designed so that the control electrodeitself generates, in response to incident light, a second signal chargecorresponding to the incident light. Also, the control signal issupplied to the transfer unit to transfer the first signal charge to thecontrol electrode such that the first and second signal charges arecombined in the control electrode, so that the output unit outputs anelectric signal corresponding to the sum of the first and second signalcharges. Alternatively, the control signal is supplied to the transferunit to transfer the first signal charge to the control electrode suchthat the first and second signal charges are present individually andsuccessively in the control electrode, so that the output unit outputsan output signal corresponding to the first signal charge and anotheroutput signal corresponding to the second signal charge.

In this first aspect of the invention, the second signal chargegenerated by the control electrode of the amplification transistor maybe added to the first signal charge generated by the photoelectricconversion element, and an electric signal corresponding to the sum ofthem may be output. This arrangement allows the area which is capable ofphotoelectric conversion to be increased in each of the photoelectricconversion devices (i.e., in each pixel) and, as a result, thephotoelectric conversion efficiency is improved.

An output signal corresponding to the second signal charge may bemonitored as the second signal charge accumulates, regardless of whetherthe first and second signal charges are combined for output.Accordingly, the brightness of the surroundings can be monitored basedon the second signal charge and the amount of signal charge beinggenerated in the photoelectric conversion element can be estimated basedon the monitoring result. As a further alternative, the first and secondsignal charges may be combined at the control electrode even as they areaccumulating, so that the total accumulated charge may be monitored viaan output signal from the output unit.

The amplification transistor of the output unit is preferably afield-effect transistor.

A color filter of a specific color may be installed above thelight-receiving surface of the control electrode of the amplificationtransistor and/or above the light-receiving surface of the photoelectricconversion element. Also, color filters of different colors may beinstalled above the light-receiving surfaces of the control electrode ofthe amplification transistor and the photoelectric conversion element.This affords various possibilities for monitoring exposure based onspecific color components, and for imaging based on specific colorcomponents.

By using a color filter of a specific color, the spectral component ofthat specific wavelength is detected by the photoelectric conversionelement, while the control electrode of the amplification transistordetects light having the same or a wider range of wavelength in order tomonitor the quantity of signal charge generated by the photoelectricconversion element.

If two color filters having different colors are used, the photoelectricconversion element detects the spectral component of one of the specificwavelengths (colors), while the control electrode of the amplificationtransistor detects the spectral component of the other specificwavelength. This arrangement allows the intensities of light componentshaving specific wavelengths to be detected based on the spectralcharacteristics (i.e., color information) of the incident light.

In another aspect of the invention, a second representative embodimentof a photoelectric conversion apparatus comprises one or more of thephotoelectric conversion devices described above, a shutter, and acontroller for controlling the timing of the shutter based on the signalcharge generated by the control electrode of the amplificationtransistor, in order to adjust the time during which the photoelectricconversion element generates a charge. The desired exposure level forthe photoelectric conversion elements may thus be estimated based on themonitored accumulation of second signal charges.

In still another aspect of the invention, a third representativeembodiment of a photoelectric conversion apparatus comprises one or moreof the photoelectric conversion devices described above, a shutter, anda controller for controlling the timing of the shutter based on the sumof the second signal charge generated by the control electrode of theamplification transistor and the first signal charge generated by thephotoelectric conversion element, in order to adjust the time duringwhich the photoelectric element generates a charge. The desired exposurelevel of the photoelectric conversion elements may thus be monitoreddirectly, and the shutter may be closed when the desired level isreached.

In another aspect of the invention, a fourth representative embodimentof a photoelectric conversion device comprises a photoelectricconversion element for generating, in response to incident light, afirst signal charge corresponding to the incident light; an output unitcomprising an amplification transistor with a control electrode foroutputting an electric signal corresponding to charge present in thecontrol electrode; a transfer unit for transferring the signal chargegenerated by the photoelectric conversion element to the controlelectrode; a reset transistor for removing from the control electrodethe charge present in the control electrode; and signal lines forproviding control signals to both the reset transistor and the transferunit.

As a feature of this aspect of the invention, the reset transistor isdesigned so that at least one of its main electrodes generates, inresponse to incident light, a second signal charge corresponding to theincident light. Further, the control signals are provided to the resettransistor and the transfer unit such that the transfer unit transfersthe first signal charge to the control electrode so that an outputsignal corresponding to the first signal charge is output by the outputunit, and so that the second signal charge is output from the at leastone of the main electrodes of the reset transistor.

The second signal charge need not be output from the at least one of themain electrodes of the reset transistor. Instead, the control signalscan be provided to the transfer unit and the reset transistor such thatthe first and second signal charges are both transferred to the controlelectrode, either so as to be individually and successively present atthe control electrode, or so as to be combined at the control electrode.Output signals corresponding to the first and second signal charges(individually or combined [added together], as the case may be) are thusoutput by the output unit.

If the selected main electrode (that is, the said one of the mainelectrodes) is used to output a signal charge, it may be connected to afirst transistor for outputting the signal charge, and to a secondtransistor for applying a prescribed voltage to this main electrode.

The reset transistor is preferably a MOS transistor.

If the first and second charges are combined, the light-sensitive areain each photoelectric device (each pixel) of a photoelectric apparatusmay be increased. If the first and second charges are output separately,they may be used to monitor the spectral content of the incident light,by the use of color filters.

A color filter of a specific color may be installed above thelight-receiving surface of the said one of the main electrodes of thereset transistor and/or above the light-receiving surface of thephotoelectric conversion element. Also, color filters having differentcolors may be installed above the light-receiving surfaces of the saidone of the main electrodes of the reset transistor and the photoelectricconversion element. Use of such filters allows the advantages mentionedabove for embodiments having such filters.

In yet another aspect of the invention, a fifth representativeembodiment of a photoelectric conversion apparatus comprises one or moreof the photoelectric conversion devices having a reset transistor asdescribed above, a shutter unit, and a controller for controlling thetiming of the shutter unit based on the second signal charge generatedby the said one of the main electrodes of the reset transistor, in orderto adjust the time during which the photoelectric element generates acharge. The desired exposure level for the photoelectric conversionelements of the photoelectric conversion devices may thus be estimatedby monitoring the accumulation of the second signal charges in the saidones of the main electrodes of the reset transistors.

In still another aspect of the invention, a sixth representativeembodiment of a photoelectric conversion device comprises aphotoelectric conversion element for generating, in response to incidentlight, a first signal charge corresponding to the incident light; anoutput unit comprising an amplification transistor with a controlelectrode for outputting an electric signal corresponding to chargepresent at the control electrode; a transfer unit for transferring thesignal charge generated by the photoelectric conversion element to thecontrol electrode; a reset transistor for removing, from the controlelectrode, the charge present at the control electrode; and signal linesfor providing control signals to both the reset transistor and thetransfer unit.

In this aspect of the invention, the amplification transistor isdesigned so that the control electrode generates, in response toincident light, a second signal charge corresponding to the incidentlight. The reset transistor is designed so that at least one of its mainelectrodes generates, in response to incident light, a third signalcharge corresponding to the incident light.

Control signals are supplied to the transfer unit and to the resettransistor such that the first signal charge is transferred to thecontrol electrode so that the output unit outputs a signal correspondingto the first signal charge, and such that the second signal charge istransferred to the at least one of the main electrodes of the resettransistor for output from the at least one of the main electrodes,either separately, or combined with (added to), the third signal charge.

The control signals may be supplied to the transfer unit and to thereset transistor such that the second and first signal charges areoutput, either together or individually, via the control electrode andthe output unit, and such that the third signal charge is output via theat least one of the main electrodes of the reset transistor.

The first, second, and third signal charges may all be transferred tothe control electrode for output via the output unit, all together (allcombined or added at the control electrode), all individually, or in anydesired subcombination.

In the embodiments in which first, second, and third signal charges aregenerated, a color filter of a specific color may be installed above atleast one light-receiving surface from among the light-receivingsurfaces of the control electrode of the amplification transistor, theone of the main electrodes of the reset transistor, and thephotoelectric conversion element. Also, color filters of differentcolors may be installed above any two or all three of thelight-receiving surfaces of (1) the control electrode of theamplification transistor, (2) the one of the main electrodes of thereset transistor, and (3) the photoelectric conversion element.

In yet another aspect of the invention, a seventh representativeembodiment of a photoelectric conversion apparatus comprises (1) one ormore of the photoelectric conversion devices, described above, thatgenerate first, second and third signal charges, (2) a shutter, and (3)a controller for controlling the timing of the shutter based on thesecond signal charge generated by the control electrode of theamplification transistor, or based on the third signal charge generatedby the said one of the main electrodes of the reset transistor, or both,in order to adjust the time during which the photoelectric conversionelement generates a charge.

The controller preferably closes the shutter when the electric signaloutput from the output unit (corresponding to the accumulated secondsignal charge) exceeds a first prescribed value, or when the thirdsignal charge output from the said one of the main electrodes of thereset transistor exceeds a second prescribed value, whichever is first,thereby adjusting the time during which the photoelectric conversionelement generates a charge.

The above and other objects, features, and advantages of the presentinvention will be apparent from the detailed description given below byway of non-limiting exemplary embodiments of the present invention, withreference to the following drawings:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a photoelectric conversion device 120 accordingto a first embodiment of the invention.

FIG. 2 is a cross-sectional view taken along the line X--X shown in FIG.1.

FIG. 3 is a cross-sectional view taken along the line Y--Y shown in FIG.1.

FIG. 4 is a circuit diagram showing the photoelectric conversion device120 and a signal detection circuit 1290.

FIG. 5 is a schematic block diagram of a photoelectric conversionapparatus 1200 which uses the photoelectric conversion device 120 as alight-receiving device 1200B.

FIG. 6 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to the photoelectric conversion device120 of FIG. 1.

FIG. 7 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to the photoelectric conversion device120 of FIG. 1 in the presence of higher-intensity incident light.

FIG. 8 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to a modified version of thephotoelectric conversion device 120 of FIG. 1.

FIG. 9 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to another modified version of thephotoelectric conversion device 120 of FIG. 1.

FIG. 10 is a circuit diagram showing a photoelectric conversion device130 and a signal detection circuit 1390 according to a second embodimentof the invention.

FIG. 11 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to the photoelectric conversion device130 of FIG. 10.

FIG. 12 is a plan view showing the structure of a photoelectricconversion device 140 according a third embodiment of the invention.

FIG. 13 is a cross-sectional view taken along the line X--X shown inFIG. 12.

FIG. 14 is a cross-sectional view taken along the line Y--Y shown inFIG. 12.

FIG. 15 is a circuit diagram showing the photoelectric conversion device140 and a signal detection circuit 1490.

FIG. 16 is a schematic block diagram of a photoelectric conversionapparatus 1400 which uses the photoelectric conversion device 140 as alight-receiving device 1400B.

FIG. 17 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to the photoelectric conversion device140 of FIG. 12.

FIG. 18 is a plan view showing the structure of a photoelectricconversion device 150 according to a fourth embodiment of the invention.

FIG. 19 is a cross-sectional view taken along the line X--X shown inFIG. 18.

FIG. 20 is a cross-sectional view taken along the line Y--Y shown inFIG. 18.

FIG. 21 is a circuit diagram showing the photoelectric conversion device150 and a signal detection circuit 1590.

FIG. 22 is a schematic block diagram of a photoelectric conversionapparatus 1500 which uses the photoelectric conversion device 150 as alight-receiving device 1500B.

FIG. 23 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to the photoelectric conversion device150 of the fourth embodiment;

FIG. 24 is a timing chart showing the waveforms of driving pulses φTG,φRSG, and φRSD which are supplied to the photoelectric conversion device150 of FIG. 18.

FIG. 25 shows an example embodiment of a single pixel of an image sensorarray useful in the context of the present invention. FIG. 25(a) is aplan view, FIG. 25(b) is a cross-sectional view taken along the lineX1-X2 in FIG. 25(a), and FIG. 25(c) is a cross-sectional view takenalong the line Y1-Y2 in FIG. 25(a).

FIG. 26 comprises circuit diagrams of equivalent circuits of pixelsuseful in the context of the present invention. FIG. 26(a) correspondsto the pixel of FIG. 25, and FIGS. 26(b) and 26(c) to modificationsthereof.

FIG. 27 shows another example embodiment of a single pixel of an imagesensor array useful in the context of the present invention. FIG. 27(a)is a plan view, FIG. 27(b) is a cross-sectional view taken along theline X3-X4 in FIG. 27(a), and FIG. 27(c) is a cross-sectional view takenalong the line Y3-Y4 in FIG. 27(a).

FIG. 28 comprises circuit diagrams of equivalent circuits of pixelsuseful in the context of the present invention. FIG. 28(a) correspondsto the pixel of FIG. 27, and FIGS. 28(b), 28(c), and 28(d) correspond tomodifications thereof.

FIG. 29 shows another example embodiment of a single pixel of an imagesensor array useful in the context of the present invention. FIG. 29(a)is a plan view, FIG. 29(b) is a cross-sectional view taken along theline X5-X6 in FIG. 29(a), and FIG. 29(c) is a cross-sectional view takenalong the line Y5-Y6 in FIG. 29(a).

FIG. 30 comprises circuit diagrams of equivalent circuits of pixelsuseful in the context of the present invention. FIG. 30(a) correspondsto the pixel of FIG. 29, and FIGS. 30(b), 30(c), and 30(d) correspond tomodifications thereof.

FIG. 31 shows yet another example embodiment of a single pixel of animage sensor array useful in the context of the present invention. FIG.31(a) is a plan view, FIG. 31(b) is a cross-sectional view taken alongthe line X7-X8 in FIG. 30(a), and FIG. 30(c) is a cross-sectional viewtaken along the line Y7-Y8 in FIG. 30(a).

FIG. 32 is a cross-sectional view taken along the line Y9-Y10 in FIG.30(a).

FIG. 33 shows still another example embodiment of a single pixel of animage sensor array useful in the context of the present invention. FIG.33(a) is a plan view, FIG. 33(b) is a cross-sectional view taken alongthe line X11-X12 in FIG. 33(a), and FIG. 33(c) is a cross-sectional viewtaken along the line Y11-Y12 in FIG. 30(a).

FIG. 34 is a cross-sectional view taken along the line Y13-Y14 in FIG.33(a).

FIG. 35 is shows still another example embodiment of a single pixel ofan image sensor array useful in the context of the present invention.FIG. 35(a) is a plan view, FIG. 35(b) is a cross-sectional view takenalong the line X15-X16 in FIG. 33(a), and FIG. 33(c) is across-sectional view taken along the line Y15-Y16 in FIG. 30(a).

FIG. 36 is a cross-sectional view taken along the line Y17-Y18 in FIG.35(a).

FIG. 37 is a circuit diagram of an equivalent circuit of an exampleembodiment of an image sensor array of the present invention.

FIG. 38 is a schematic diagram of elements of an example embodiment of afixed-image image capture apparatus of the present invention utilizingthe image sensor array of FIG. 37 as image sensor array 100.

FIG. 39 is a timing chart illustrating the operation of the fixed-imagecapture apparatus of FIG. 38.

FIG. 40 is a schematic diagram of elements of another example embodimentof a fixed-image image capture apparatus of the present invention.

FIG. 41 is a timing chart illustrating the operation of the fixed-imagecapture apparatus of FIG. 40.

FIG. 42 is a circuit diagram of an equivalent circuit of another exampleembodiment of an image sensor array of the present invention.

FIG. 43 shows an example embodiment of on-chip microlenses for use withthe present invention. FIG. 43(a) is a plan view, and FIG. 43(b) is across-sectional view taken along the line A-A' in FIG. 43(a).

FIG. 44 shows another example embodiment of on-chip microlenses for usewith the present invention. FIG. 44(a) is a plan view, and FIG. 44(b) isa cross-sectional view taken along the line A-A' in FIG. 44(a).

FIG. 45 is a plan view of yet another example embodiment of on-chipmicrolenses for use with the present invention.

FIG. 46 shows still another example embodiment of on-chip microlensesfor use with the present invention. FIG. 46(a) is a plan view, and FIG.46(b) is a cross-sectional view taken along the line A-A' in FIG. 46(a).

FIG. 47 is a schematic diagram of an aperture-ratio compensation systemfor use in the present invention.

FIG. 48 is a flow diagram illustrating the basic operation of the systemof FIG. 47.

FIG. 49 (prior-art) is a plan view showing the structure of aconventional photoelectric conversion device 110.

FIG. 50 (prior-art) is a cross-sectional view taken along the line X--Xline shown in FIG. 25.

FIG. 51 (prior-art) is a cross-sectional view taken along the line Y--Yshown in FIG. 25.

FIG. 52 (prior-art) is a circuit diagram showing the conventionalphotoelectric conversion device 110 and a conventional signal detectioncircuit 1190.

FIG. 53 (prior-art) is a timing chart showing the waveforms of drivingpulses φTG, φRSG, and φRSD which are supplied to the conventionalphotoelectric conversion device 110.

FIG. 54 (prior art) shows a conventional pixel similar to that of FIG.49, but structured and arranged to be part of a two-dimensional matrixof such pixels in an image sensor array. FIG. 54(a) is a plan view, FIG.54(b) is a cross-sectional view taken along the line X19-X20 in FIG.54(a), and FIG. 54(c) is a cross-sectional view taken along the lineY19-Y20 in FIG. 54(a).

FIG. 55 (prior art) is a circuit diagram of an equivalent circuit of animage sensor array employing pixels such as the pixel of FIG. 54.

FIG. 56 (prior art) shows know microlenses as employed on a CCD-typeimage sensor array. FIG. 56(a) is a plan view, and FIG. 56(b) is across-sectional view taken along the line A-A' in FIG. 56(a).

DETAILED DESCRIPTION Photoelectric Conversion Device Example Embodiment1

The first example embodiment of the invention is described below withreference to FIGS. 1 through 7.

The structure of the photoelectric conversion device 120 according tothe first embodiment is shown in FIGS. 1 through 3, where FIG. 1 is aplan view, FIG. 2 is a cross-sectional view taken along the line X--Xshown in FIG. 1, and FIG. 3 is a cross-sectional view taken along theline Y--Y shown in FIG. 1. FIG. 4 is a circuit diagram showing thephotoelectric conversion device 120 and a signal detection circuit 1290connected to the photoelectric conversion device 120. FIG. 5 is aschematic block diagram of a photoelectric conversion apparatus 1200which uses the photoelectric conversion device 120 as a light-receivingdevice 1200B, and FIGS. 6 and 7 are timing charts that may be used toexplain the operation of the photoelectric conversion device 120.

The photoelectric conversion device 120 comprises a photodiode (i.e., aphotoelectric conversion element) 121 for generating a signal chargecorresponding to the incident light; a junction field-effect transistor(i.e., an amplification transistor; referred to as a JFET) 122 foroutputting an electric signal (Vout) according to the signal chargesupplied to its gate region (i.e., a control electrode) 122A; a P-typetransfer transistor 123 (i.e., a transfer unit) for supplying ortransferring the signal charge generated and accumulated in thephotodiode 121 to the gate region 122A; and a P-type reset transistor124 for removing the signal charge supplied to the gate region 122A. Inthis photoelectric conversion device 120, the JFET serves, together witha vertical signal line 1228 and associated circuit components, as anoutput unit.

As shown in FIGS. 1 through 3, the light-blocking film (e.g., thelight-blocking aluminum layer) which typically covers the entiresemiconductor area except for the photodiode 121, is selectively removedfrom the gate region 122A of the JFET 122 so that light strikes the gateregion 122A.

When light is incident on the photoelectric conversion device 120, notonly the photodiode 121 (as a primary light-receiving element), but alsothe semiconductor area that comprises the gate region 122A (as asecondary light-receiving element) generates a signal chargecorresponding to the incident light. In other words, the JFET 122functions as a second photoelectric conversion device in thisembodiment. When a signal charge is generated in the gate region 122A inresponse to the incident light, an electric signal Vout2 correspondingto this signal charge occurs at the source region because of theoperation of the JFET 122, the details of which will be described later.

In this arrangement, by controlling the timing of the transfer of thesignal charge from the photodiode 121 (i.e., the primary light-receivingelement) to the gate region 122A (i.e., the secondary light-receivingelement), an electric signal Vout1, which corresponds to the signalcharge generated and accumulated in the photodiode 121, and an electricsignal Vout2, which corresponds to the signal charge generated by thegate region 122A of the JFET 122, may be output separately. As analternative, by appropriate control of the timing of the transfer of thesignal charge from the photodiode, the separately generated signalcharges may be combined, and an electric signal Vout corresponding tothe sum of the two signal charges can be output.

First, the arrangement in which the electric signal Vout1 and theelectric signal Vout2 are separately output will be explained.

In this arrangement, the electric signal Vout2 which represents thesignal charge generated by the gate region 122A of the JFET 122 is usedto control the shutter-open time (i.e., the exposure time) of a shutter1200C of a photoelectric conversion apparatus 1200 that employs thephotoelectric conversion device 120. To be more precise, the amount ofsignal charge generated and accumulated in the photodiode 121, whichrepresents the intensity of the incident light, is monitored based onthe amount of signal charge generated in the gate region 122A, and theexposure time is controlled based on the monitoring result (usingVout2).

The structure of the photoelectric conversion device 120 according tothis embodiment will now be explained in more detail, with reference toFIGS. 1 through 3.

As shown in FIGS. 2 and 3, the photodiode 121, the JFET 122, the P-typetransfer transistor 123, and the P-type reset transistor 124, whichconstitute the photoelectric conversion device 120, are provided on anN-type semiconductor layer 1202 formed on a P-type semiconductorsubstrate 1201. The photodiode 121, the JFET 122, the transfertransistor 123, and the reset transistor 124 are surrounded by ahigh-density N⁺ -type impurity diffusion layer 1203, as shown in FIG. 1.

The photodiode 121 consists of a P-type impurity diffusion layer (i.e.,a charge accumulation region) 1212 formed in the N-type semiconductorlayer 1202, and a high-density N⁺ -type impurity diffusion layer 1213formed on the P-type impurity diffusion layer 1212.

The signal charge generated in response to the light incident on thephotodiode 121 is accumulated in the P-type impurity diffusion layer(i.e., charge accumulation region) 1212.

The JFET 122 consists of a P-type impurity diffusion layer 1221 formedin the N-type semiconductor layer 1202, which becomes a gate region122A; an N-type impurity diffusion layer 1222 formed in the P-typeimpurity diffusion layer 1221, which becomes a source; an N-typeimpurity diffusion layer 1223 formed in the same P-type impuritydiffusion layer 1221, which becomes a channel; and a portion of N-typeimpurity diffusion layer 1203 facing the N-type impurity diffusion layer1222 with the N-type impurity diffusion layer 1223 sandwiched betweenthem, which becomes a drain.

The signal charge generated and accumulated in the photodiode 121 issupplied (or transferred) to the gate region 122A of the JFET 122 viathe transfer transistor 123 shown in FIG. 3, and an electric signalcorresponding to the supplied signal charge is output from the source ofthe JFET 122.

As shown in FIGS. 2 and 3, the gate region 122A of JFET 122 sandwichesthe channel region 1223 from above and below in order to increase thegain of the source-follower action, while reducing the variation of thegain.

The transfer transistor 123 comprises a source, which consists of thecharge accumulation region (i.e., the P-type impurity diffusion layer)1212 of the photodiode 121, and a drain, which consists of the gateregion 122A (i.e., the P-type impurity diffusion layer 1221) of the JFET122. A gate is formed between the above source and drain by a gateelectrode (i.e., a transfer gate) 123C together with the N-typesemiconductor layer 1202, separated by an insulating film 1209, as shownin FIG. 3.

As has been described above, the transfer transistor 123 transfers thesignal charge accumulated in the P-type charge accumulation region(i.e., the P-type impurity diffusion layer) 1212 of the photodiode 121to the gate region 122A of the JFET 122.

The reset transistor 124 comprises a source, which consists of the gateregion 122A (i.e., the P-type impurity diffusion layer 1221) of the JFET122, and a reset drain, which consists of the P-type impurity diffusionlayer 1241. A gate electrode (i.e., a reset gate) 124C is positionedbetween the source and the reset drain, above the N-type semiconductorlayer 1202 and separated therefrom by a gate insulating film, as shownin FIG. 2.

The reset transistor 124 resets the potential of the gate region 122A ofthe JFET 122 to the readout level VGH.

Since the voltage of the gate region 122A of the JFET 122 is brought tothe constant voltage VGH upon the reset action, the charge that has beenaccumulated in the gate region 122A is removed, and it is not reflectedin the output (i.e., the source voltage) of the JFET 122 any longer. Atthis time, an electric signal VD, corresponding to the constant voltageVGH at the gate region 122A, is output. This electric signal VDcorresponds to the dark output of the photoelectric conversion device120.

As shown in FIG. 3, a color filter (for example, a blue filter) 125 isprovided above the light-receiving surface of the photodiode 121 in thephotoelectric conversion device 120, whereby a signal charge reflectingthe intensity of the blue spectral component of the incident light isgenerated in the photodiode 121.

The photoelectric conversion device 120 also includes a vertical signalline 1228, a transfer gate interconnection 1238, a reset gateinterconnection 1247, and a reset drain interconnection 1248, as shownin FIGS. 1-3.

Next, the circuit structure of the photoelectric conversion device 120and the signal detection circuit 1290 connected to the photoelectricconversion device 120 will be explained with reference to FIG. 4. Inaddition, the structure of the photoelectric conversion apparatus 1200using the photoelectric conversion device 120 as a light-receiving unit1200B will be described with reference to FIG. 5, and the operation ofthis apparatus will be explained using the timing charts shown in FIGS.6 and 7.

As shown in FIG. 4, in the photoelectric conversion device 120, thephotodiode 121, which functions as the primary light-receiving element,is connected to a constant voltage source VDD, and a reverse bias isapplied. The constant voltage source VDD is also connected to the drainof the JFET 122, as shown.

A driving pulse φTG is supplied from a driving circuit (not shown) tothe gate electrode (i.e., transfer gate) 123C of the transfer transistorQTG (1023).

A driving pulse φRSG is supplied to the gate electrode (i.e., resetgate) 124C of the reset transistor QRSG (1024), and a driving pulse φRSDis supplied to a drain (i.e., the reset drain) 124B from the drivingcircuit (not shown).

The source (the node N1 side) of the JFET 122 is connected to a constantvoltage source VSS via a constant-current source which supplies aconstant current Ibias to the source of the JFET 122, thereby allowing asource-follower action.

In this photoelectric conversion device 120, the source voltage Vout(i.e., the voltage at the node N1) of the JFET 122 becomes an electricsignal obtained by current amplification for amplifying the signalcharge accumulated in the gate region 122A, based on source-followeraction. If the signal charge held in the gate region 122A of the JFET122 is the signal charge generated by the photodiode (i.e., the primarylight-receiving element) 121, the output electric signal is Vout1, whichindicates the intensity of the incident light detected by the photodiode121. On the other hand, if the signal charge held in the gate region122A is the charge accumulated directly in the gate region 122A, theoutput electric signal is Vout2, which indicates the intensity of theincident light detected by the gate region (i.e., secondarylight-receiving element) 122A.

By controlling the waveforms of the driving pulses φTG, φRSG, and φRSDsupplied from the driving circuit (not shown), the electric signal Voutoccurring at the source (on the node N1 side) of the JFET 122 can bemade to correspond to Vout1 at a certain time, and to Vout2 at anothertime. When the gate region 122A is reset by the reset transistor QRSG(1024), the electric signal Vout represents the dark output of thephotoelectric conversion device 120.

The source (the node N1) of the JFET 122 is connected to the signaldetection circuit 1290, and the electric signal Vout is supplied fromthe source of the JFET 122 to the signal detection circuit 1290.

The signal detection circuit 1290 has a sample-and-hold circuit 1291 anda difference calculation circuit 1292. The reference signal voltage VD,which corresponds to the dark output, is held by the sample-and-holdcircuit 1291. The difference calculation circuit 1292 subtracts thisreference voltage VD from Vout1 (also referred to as Vs) whichrepresents the signal charge generated by the photodiode 121. Differencecalculation circuit thus produces photosignal Vp, from which the darkoutput has been removed.

FIG. 5 shows the overall structure of the photoelectric conversionapparatus 1200 using the photoelectric conversion device 120 as alight-receiving device 1200B.

The light-receiving device 1200B is comprised of the photoelectricconversion device 120 (and may include an array of such devices) and thedriving circuit (not shown), and it is accommodated in a dark box 1200A.A shutter 1200C is fit into an opening of the dark box 1200A, throughwhich light comes in the direction indicated by the arrow.

A controller 1200D, a comparator 1280, and the signal detection circuit1290 are connected to the light-receiving device 1200B accommodated inthe dark box 1200A.

The controller 1200D outputs a control signal to the driving circuit(not shown) in order to cause the driving circuit to supply the drivingpulses φTG, φRSG, and φRSD to the photoelectric conversion device 120.

The comparator 1280 is connected to the controller 1200D. The comparator1280 compares the electric signal Vout2, which corresponds to the signalcharge generated by the gate region 122A of the JFET 122, with thereference signal Vref, and outputs a signal representing the comparisonresult to the controller 1200D.

The controller 1200D supplies a control signal SH to the shutter 1200Cbased on the comparison signal received from the comparator 1280,thereby controlling the shutter-open time (i.e., the exposure time).

Next, the operation of the photoelectric conversion device 120 duringthe detection of the incident light will be explained using the timingcharts shown in FIGS. 6 and 7. For ease of explanation, a single cycleof operation from t10 to t20 will be used.

As shown in FIG. 6, the shutter 1200C has been closed based on thecontrol signal SH being set high (high being closed, low being open) bythe controller 1200D before t10. Just before t10 the driving pulse φTGis at a high level, the driving pulse φRSD is at a low level, and thedriving pulse φRSG is at a high level. Because the signal chargegenerated by the photodiode 121 has been transferred to the gate region122A of the JFET 122 before t10, the electric signal Vout1 occurring atthe node N1 has a value Vs corresponding to the incident light of theprevious cycle.

At t10, the driving pulse φRSD is changed from the low level to the highlevel (i.e., the readout level VGH), and the driving pulse φRSG ischanged from the high level to the low level.

Upon the change of the driving pulse φRSG to the low level, the P-typereset transistor QRSG is turned on. Upon the change of the driving pulseφRSD to the readout level (VGH), a constant voltage VGH is applied tothe drain of the reset transistor QRSG, and to the gate region 122A ofthe JFET 122, resetting the gate region 122A.

At t11, the control signal SH supplied from the controller 1200D becomeslow, and the shutter 1200C is opened, whereby exposure starts. Also att11, the driving pulse φRSD returns to the low level, and the drivingpulse φRSG returns to the high level, whereby the reset state of thegate region 122A of the JFET 122 is terminated.

At t11, the driving pulse φTG remains at the high level, and thetransfer transistor QTG is still in the OFF state. Accordingly, thesignal charge generated in the photodiode 121 upon the start of theexposure time is accumulated in the photodiode 121, and it is notsupplied to the gate region 122A of the JFET 122.

Because the shutter 1200C is opened at t11, the gate region 122A alsogenerates a signal charge in response to the incident light. This signalcharge generated by the gate region 122A produces a corresponding outputin the signal Vout occurring at the source (node N1) of the JFET 122,and that corresponding output signal is referred to as Vout2.

The value of the electric signal Vout2 gradually increases while theshutter 1200C is open (t11 to t12). When the electric signal Vout2reaches the reference value Vref at t12, the control signal SH suppliedfrom the controller 1200D to the shutter 1200C is changed to the highlevel, and the shutter 1200C is closed (i.e., the exposure time ends).

If the intensity of the light incident to the gate region 122A is low,the value of the electric signal Vout2 increases with a gentle slopefrom t11 to t12, as shown in FIG. 6, and the time interval between t11and t12 is relatively long, which means that the exposure time is long.

On the other hand, if the intensity of the light incident to the gateregion 122A is high, the value of the electric signal Vout2 increasesrapidly from t11 to t12, as shown in FIG. 7, and the electric signalVout2 reaches the reference value Vref in a short time. Thus, theexposure time is short.

When the electric signal Vout2 representing the signal charge generatedby the gate region 122A reaches the reference value Vref at t12, theshutter 1200C is closed (upon the change of the control signal SH to thehigh level), the driving pulse φRSG becomes low, and the driving pulseφRSD becomes the readout level (the constant voltage VGH).

Upon the change of the driving pulse φRSG to the low level, the resettransistor QRSG is turned on, and the reset drain 124B achieves theconstant voltage VGH (reset action). At this time, the electric signalVout at the source of the JFET 122 has the value of the reference signalvoltage VD, which corresponds to the dark output.

At t13, the driving pulse φRSD is again changed to the low level, andthe driving pulse φRSG is again changed to the high level. Although thegate region 122A of the JFET 122 is thus put into a floating state, thevalue of the electric signal Vout occurring at the node N1 remains atVD.

At t14, the driving pulse φTG is changed to the low level, and thetransfer transistor QTG is turned on. When the transfer transistor QTGis turned on, the signal charge generated and accumulated in thephotodiode 121 during the period from t11 to t12 is transferred to thegate region 122A of the JFET 122.

At t15, the driving pulse φTG is again changed to the high level, andthe transfer transistor QTG is turned off. At this time, the value ofthe electric signal Vout1 occurring at the source (node N1) of the JFET122 remains at Vs, which corresponds to the signal charge generated andaccumulated in the photodiode 121.

At t20, the driving pulse φRSD again reaches the readout level (i.e.,the constant voltage VGH), and the driving pulse φRSG is changed fromthe high level to the low level.

Upon the change of the driving pulse φRSG to the low level, the P-typereset transistor QRSG is turned on again. At the same time, upon thechange of the driving pulse φRSD to the readout level (VGH), theconstant voltage VGH is applied to the drain of the P-type resettransistor QRSG, and the value of the electric signal Vout occurring atthe node N1 becomes the reference signal voltage VD, which correspondsto the dark output.

The operations from t10 through t20 (that is, one cycle ofincident-light-detection operations) are repeated in the subsequentprocess.

The electric signal VD obtained in the period from t12 to t14 is storedand held by the sample-and-hold circuit 1291 shown in FIG. 4. Thedifference calculation circuit 1292 subtracts this value VD from theelectric signal Vs obtained in the period from t14 to t20, yielding anelectric signal Vp, from which the noise component VD, due to darkcurrent fluctuation, is removed.

In the photoelectric conversion device 120 according to this firstembodiment, light can strike the gate region 122A of the JFET 122, andthe signal charge generated by the gate region 122A is output as anelectric signal Vout from the source (node N) of the JFET 122.

Accordingly, if this photoelectric conversion device 120 is used as thelight-receiving device 1200B of a photoelectric conversion apparatus1200, an appropriate exposure time for the photodiode 121 can be setbased on the signal charge generated by the gate region 122A. In otherwords, the brightness of the surroundings during the process ofphotographing is monitored based on the signal charge generated by thegate region 122A, and the electric signal Vout2 representing the signalcharge generated by the gate region 122A is compared with the referencevalue Vref in order to adjust the shutter-open time of the shutter1200C, whereby the optimal exposure time can be selected according tothe brightness of the surroundings during the exposure.

Signal charges are generated in both the photodiode 121, which is theprimary light-receiving element, and the gate region 122A of the JFET122, which is the secondary light-receiving element. In this embodiment,a color filter (e.g., a blue filter) 125 is provided above thelight-receiving surface of the photodiode 121, as shown in FIG. 3. Byproviding the color filter 125 above the light-receiving surface of thephotodiode 121, the color component defined by the color filter 125(i.e., the blue component in this example) is extracted from theincident light, and is detected by the photoelectric conversion device120.

With the photoelectric conversion apparatus 1200 using the photoelectricconversion device 120, the exposure time is determined based on thesignal charge (Vout2) generated by the gate region 122A. However, thelight-receiving area of the gate region 122A is smaller than that of thephotodiode 121 which is the primary light-receiving element.

For this reason, in the first embodiment, the color filter 125 is placedonly above the photodiode 121 in order to allow the gate region 122A toreceive a sufficient quantity of light. In this arrangement, thephotosensitivity of the gate region 122A is improved in spite of therelatively small light-receiving area, resulting in an increased amountof signal charge generated in this region. Consequently, the exposuretime is adjusted with a high degree of precision.

Of course, a color filter having a specific color (e.g., blue) may beplaced above the light-receiving surfaces of both the photodiode 121 andthe gate region 122A of the JFET 122. In this case, the gate region 122Acan detect the same color component of the incident light as thatdetected by the photodiode 121. Thus, the signal charge generated by thephotodiode 121 can be monitored by extracting a specific color component(e.g., the blue component) from the incident light, and the exposuretime can be adjusted to the optimal value for detecting the intensity oflight having a specific color component (e.g., blue).

As another alternative, color filters having different colors may beprovided above the light-receiving surfaces of the photodiode 121 andthe gate region 122A of the JFET 122. For example, a blue filter may beplaced above the photodiode 121, and a red filter above the gate region122A.

Providing color filters of different colors above the light-receivingsurfaces of both the photodiode 121 and the gate region 122A of the JFET122 has the advantage of allowing the spectral characteristics of theincident light to be detected.

Depending on the circumstances, a certain amount of the spectralcharacteristics (i.e., color information) of the incident light may berequired when detecting light using the photoelectric conversion device120. For example, in spectrophotometry, the properties of an object aremeasured by illuminating the object with light having a specificwavelength and detecting the radiation from the object.

For example, if the object is illuminated with red light, and if theobject then radiates blue light, in addition to red light which is thesame color as the incident light, the intensity ratio of the radiatedred light to the radiated blue light may be obtained by use of thephotoelectric conversion device 120.

For example, if the intensity of the radiated red light is strong, ablue filter is placed above the light-receiving surface of thephotodiode which has a relatively large light-receiving area, and a redfilter is placed above the light-receiving surface of the gate region122A of the JFET 122, whereby the intensity ratio of the red spectralcomponent to the blue spectral component can be detected with a highdegree of accuracy.

As still another alternative, a color filter (for example, a red filter)may be placed only above the light-receiving surface of the gate region122A of the JFET 122, without providing any color filters above thelight-receiving surface of the photodiode 121.

In this case, the photodiode 121 detects the intensity of the incidentlight, which contains various color components, and the gate region 122Adetects a specific color component of the incident light. The spectralcharacteristics (i.e., color information) of the incident light can beaccurately obtained based on the known spectral sensitivities of thelight detected by the photodiode 121 and the gate region 122A. At thesame time, the exposure time can be controlled based on the signalcharge generated by the gate region 122A.

First Modification of the First Example Embodiment

A first modification of the first example embodiment will now bedescribed using the timing chart shown in FIG. 8.

In this modification, the driving pulses φTG, φRSG, and φRSD, which aresupplied from the driving circuit (not shown) to the transfer transistorQTG, the gate electrodes of the reset transistor QRSG, and the resetdrain 124B of the reset transistor QRSG of the photoelectric conversiondevice 120 of FIG. 4, respectively, have waveforms different from thoseshown in the timing chart of FIG. 6.

With these driving pulses φTG, φRSG, and φRSD having the waveforms shownin FIG. 8, an electric signal Vout corresponding to the sum of thesignal charge generated by the gate region 122A and the signal chargegenerated by the photodiode 121 is obtained at the source (node N1) ofthe JFET 122.

For ease of explanation, a single cycle of operation (t10 to t20) ofthis modified photoelectric conversion device 120 will be explained withreference to FIG. 8.

Just before t10, the shutter 1200C has been in the closed state based onthe control signal SH supplied from the controller 1200D. The drivingpulse φTG is at a high level, the driving pulse φRSD is at a low level,and the driving pulse φRSG is at a high level. The electric signal Voutoccurring at the node N1 has a value Vs corresponding to the incidentlight of the previous cycle.

At t10, the driving pulse φRSD is raised to the readout level (VGH), andthe driving pulse φRSG is changed from the high level to the low level.

Upon the change of the driving pulse φRSG to the low level, the P-typereset transistor QRSG is turned on. Upon the change of the driving pulseφRSD to the readout level (VGH), the constant voltage VGH is applied tothe drain of the turned-on reset transistor QRSG. The electric signalVout occurring at the node N1 then becomes the reference signal voltageVD, which corresponds to the dark output.

At t11, the control signal SH supplied from the controller 1200D becomeslow, and the shutter 1200C is opened, whereby exposure starts. At thistime, the driving pulse φRSD returns to the low level, and the drivingpulse φRSG returns to the high level, whereby the gate region 122A ofthe JFET 122 is put into a floating state.

The driving pulse φTG remains high, and the transfer transistor QTG isstill in the "OFF" state. Accordingly, the signal charge generated inthe photodiode 121 upon the start of the exposure time is accumulated inthe charge accumulation region of the photodiode 121, and it is notsupplied to the gate region 122A of the JFET 122.

With the shutter 1200C open, both the photodiode 121 and the gate region122A generate signal charges in response to the incident light.Accordingly, the electric signal Vout occurring at the source (node N1)of the JFET 122 becomes Vout2, which represents the signal chargegenerated in the gate region 122A during the exposure time.

The value of the electric signal Vout2 gradually increases while theshutter 1200C is open (t11 to t12). When the electric signal Vout2reaches the reference value Vref at t12, the control signal SH suppliedfrom the controller 1200D to the shutter 1200C is changed to the highlevel, and the shutter 1200C is closed (i.e., the exposure time ends).Thus, the period from t11 to t12 is the exposure time.

The photodiode 121 generates and accumulates a signal charge in responseto the incident light during the exposure time.

When the electric signal Vout2, representing the signal charge generatedby the gate region 122A, reaches the reference value Vref at t12, theshutter 1200C is closed (upon the change of the control signal SH to thehigh level), the driving pulse φTG becomes low, and the transfertransistor QTG is turned on.

Upon turning on the transfer transistor QTG, the signal charge generatedand accumulated in the photodiode 121 in the period from t11 to t12 istransferred to the gate region 122A of the JFET 122.

Before the gate region 122A receives the signal charge supplied from thephotodiode 121, the gate region 122A is holding the signal chargegenerated by the gate region 122A itself. Accordingly, at t12, thesignal charge newly supplied from the photodiode 121 via the transfertransistor QTG is added to the signal charge generated in the gateregion 122A, and the sum of both signal charges is stored in the gateregion 122A.

At this time, the electric signal Vout occurring at the source (node N1)of the JFET 122 becomes Vs, which represents the sum of the signalcharge generated by the photodiode 121 and the signal charge generatedby the gate region 122A.

At t13, the driving pulse φTG is again changed to the high level, andthe transfer transistor QTG is turned off. Although the gate region 122Aof the JFET 122 is thus put into a floating state, the value of theelectric signal Vout at the node N1 remains at Vs.

At t20, the driving pulse φRSD is again raised to the readout level, andthe driving pulse φRSG is changed from the high level to the low level.

Upon the change of the driving pulse φRSG to the low level, the P-typereset transistor QRSG is turned on again. At the same time, upon thechange of the driving pulse φRSD to the readout level (VGH), theconstant voltage VGH is applied to the drain of the P-type resettransistor QRSG, and the gate region 122A of the JFET 122 is reset(i.e., the charge accumulated in the gate region 122A is removed).Consequently, the value of the electric signal Vout occurring at thenode N1 becomes the reference signal voltage VD, which corresponds tothe dark output.

By repeating the operations from t10 through t20, successive cycles ofthe detection operation are performed.

The electric signal VD obtained during the period t10 to t11, and theelectric signal Vs obtained during the period t12 to t20 are supplied tothe signal detection circuit 1290, and a signal corresponding to thedifference between these two signals is output as a photosignal Vp, fromwhich the noise component VD (caused, for example, by fluctuation) isremoved.

In this first modification of the first example embodiment, the signalcharge generated by the photodiode 121 and the signal charge generatedby the gate region 122A are added up, and the sum is held in the gateregion 122A. Accordingly, the electric signal Vout (that is, Vout1,which equals Vs) occurring at the source (node N1) of the JFET 122represents this sum.

Thus, the signal charge generated by the gate region 122A is used todetermine the exposure time (t11 to t12), based on a comparison with thereference value Vref, and at the same time it is also added to thesignal charge generated by the photodiode 121 and contributes to theelectric signal Vout which represents the intensity of the incidentlight during this exposure time. In the photoelectric conversion device120 which operates in this manner, the gate region 122A functions as aphotoelectric conversion element together with the photodiode 121, andthe light-receiving area in each pixel is thus substantially increased.

Since the signal detection circuit 1290 removes the noise component (VD)from the electric signal Vs generated in response to the incident light,and outputs a photosignal Vp, accurate light detection can be achieved.

As in the unmodified first example embodiment (which operates accordingto the timing chart shown in FIG. 6), the shutter-open time (i.e., theexposure time) of the photoelectric conversion apparatus 1200 iscontrolled based on the electric signal Vout2 corresponding to thesignal charge generated by the gate region 122A and, consequently, theoptimum exposure time for a given exposure can be set even if thebrightness of the surroundings changes during the exposure.

Second Modification of the First Example Embodiment

A second modification of the first embodiment will now be describedusing the timing chart shown in FIG. 9.

In this modification, the driving pulses φTG, φRSG, and φRSD (FIG. 9),which are supplied respectively to the transfer transistor QTG, the gateelectrodes of the reset transistor QRSG, and the reset drain 124B of thereset transistor QRSG of the photoelectric conversion device 120 of FIG.4, have waveforms different from those shown in the timing charts ofFIG. 6 and FIG. 8. By supplying the driving pulses φTG, φRSG, and φRSDof FIG. 9 to the transfer transistor QTG, the gate electrodes of thereset transistor QRSG, and the reset drain 124B of the reset transistorQRSG, respectively, the signal charge generated in the photodiode 121 istransferred to the gate region 122A during the exposure as it isgenerated, and is added to the signal charge generated by the gateregion 122A. Accordingly, an electric signal Vout corresponding to thesum of these two signal charges is obtained. The opening time of theshutter 1200C (i.e., the exposure time) of the apparatus 1200 iscontrolled based on the electric signal Vout and, in addition, thiselectric signal Vout, representing the sum of the signal charges is usedto produce the photosignal Vp.

For purposes of simplification, only a single cycle of operation fromt10 to t20 will be explained, as in the previous examples.

Before t10, the shutter 1200C has been in the closed state based on thecontrol signal SH supplied from the controller 1200D. The driving pulseφTG is at a high level, the driving pulse φRSD is at a low level, andthe driving pulse φRSG is at a high level. The electric signal Voutoccurring at the node N1 has a value Vs corresponding to the incidentlight of the previous cycle.

At t10, the driving pulse φRSG is changed from the high level to the lowlevel, and the P-type reset transistor QRSG is turned on. At the sametime, the driving pulse φRSD is raised to the readout level (VGH), andthe constant voltage VGH is applied to the drain of the turned-on resettransistor QRSG, whereby the gate region 122A is reset. At this time,the electric signal Vout occurring at the node N1 becomes the referencesignal voltage VD, which corresponds to the dark output.

At t11, the control signal SH supplied from the controller 1200D becomeslow, and the shutter 1200C is opened, whereby exposure starts. At thistime, the driving pulse φRSD returns to the low level, whereby the resetstate of the gate region 122A is terminated, and the driving pulse φTGbecomes low, whereby the transfer transistor QTG is turned on at thesame time as the opening of the shutter 1200C.

Upon the start of the exposure time, light strikes both the photodiode121 and the gate region 122A of the photoelectric conversion device 120,and the photodiode 121 and the gate region 122A start generating signalcharges.

During the exposure time, the signal charge generated by the photodiode121 is transferred directly to the gate region 122A via the turned-ontransfer transistor QTG, and is added to the signal charge generated bythe gate region 122A. Therefore, the value of the electric signal Voutoccurring at the source (node N1) of the JFET 122 increases steeply asboth the signal charge generated by the photodiode 121 and the signalcharge generated by the gate region 122A increase in the time intervalbetween t11 and t12 shown in FIG. 9.

When the electric signal Vout, representing the sum of the signal chargegenerated by the photodiode 121 and the signal charge generated by thegate region 122A, reaches the reference value Vref at t12, the controlsignal SH is changed to the high level, and the shutter 1200C is closed(i.e., the exposure time ends).

Also at t12, the driving pulse φTG is changed to the high level, and thetransfer transistor QTG is turned off, whereby the electric connectionbetween the gate region 122A of the JFET 122 and the photodiode 121 iscut off. As a result, the gate region 122A of the JFET 122 is put into afloating state; however, the value of the electric signal Vout occurringat the node N1 remains at Vs, which reflects the sum of the two signalcharges.

At t20, the driving pulse φRSG is changed to the low level, and theP-type reset transistor QRSG is turned on again. At the same time, thedriving pulse φRSD is raised to the readout level (i.e., the constantvoltage VGH), and this constant voltage VGH is applied to the drain ofthe P-type reset transistor QRSG (reset action). Consequently, the valueof the electric signal Vout occurring at the node N1 becomes thereference signal voltage VD, which corresponds to the dark output.

The operations from t10 through t20 are repeated to perform successivecycles of light detection.

The electric signal VD obtained during the period t10 to t11 and theelectric signal Vs obtained during the period t11 to t20 are supplied tothe signal detection circuit 1290, and a signal corresponding to thedifference between these two signals is output as a photosignal Vp,which does not contain the noise component VD (caused, for example, byfluctuation).

In this second modification of the first example embodiment, in themanner described above, the exposure time (i.e., the shutter-open time)of the photoelectric conversion apparatus 1200 is controlled by thephotoelectric conversion device 120 using both the signal chargegenerated by the gate region 122A and the signal charge generated by thephotodiode 121. Accordingly, the degree of accuracy to which theexposure time is controlled for photography can be further improved.

As in the first modification of the first example embodiment, theelectric signal Vout representing the sum of the signal charge generatedby the photodiode 121 and the signal charge generated by the gate region122A is output. Thus, the light-receiving area in each pixel issubstantially increased.

Photoelectric Conversion Device Example Embodiment 2

Next, a photoelectric conversion device 130 and a photoelectricconversion apparatus according to a second example embodiment of theinvention will be described with reference to FIGS. 10 and 11. Featuressubstantially similar or the same as those described above havereference characters the same as those described above, but this a "3"as a first digit. Where no additional description is given, the abovedescription applies to corresponding features of this exampleembodiment.

In this embodiment, the shutter-open time (i.e., the exposure time) isagain controlled based on an electric signal Vout representing thesignal charged generated by the gate region 132A of the JFET. Unlike thefirst embodiment, however, the electric signal Vout is output withoutkeeping the JFET in the ON state all the time. Accordingly, the powerconsumption can be reduced, as compared with the photoelectricconversion device 120 of the first embodiment, in which the JFET 122 iskept turned on all the time.

As shown in the circuit diagram of FIG. 10, the photoelectric conversiondevice 130 according to the second embodiment comprises a photodiode 131for generating a signal charge corresponding to the incident light; aJFET for outputting an electric signal (Vout) supplied to its gateregion 132A; a P-type transfer transistor QTG for supplying ortransferring the signal charge generated and accumulated in thephotodiode 131 to the gate region 132A; and a P-type reset transistorQRSG for removing the signal charge supplied to the gate region 132A.The source (on the node N1 side) of the JFET is connected to theconstant voltage source VSS via a capacitor C1. A second N-type resettransistor QRST is connected in series with the capacitor C1 to thesource of the JFET so that a driving pulse φRST is supplied to the gateof this reset transistor QRST from the driving circuit (not shown).

As in the photoelectric conversion device 120 of the first embodiment,there is no blocking film provided above the gate region 132A of theJFET, in order to allow the JFET to function as a phototransistor and toallow its gate region 132A to generate a signal charge in response tothe incident light. The structures of the major elements, including theJFET, of this photoelectric conversion device 130 are the same as thoseof the photoelectric conversion device 120 of the first embodiment, anddetailed explanation of them will therefore be omitted.

With the photoelectric conversion apparatus using the photoelectricconversion device 130 according to this embodiment, an electric signalVout1, which corresponds to the signal charge generated and accumulatedin the photodiode 131, and an electric signal Vout2, which correspondsto the signal charge generated in the gate region 132A of the JFET, areseparately output. The shutter-open (exposure) time is controlled basedon the signal charge generated by the gate region 132A, therebyadjusting the exposure time of the photodiode 131.

More specifically, the electric signal Vout output from the JFET firsttakes on the value Vs corresponding to the signal charge generated bythe photodiode 131, and then takes on the value VD (corresponding to adark output) during the reset state of the gate region 132A,independently of each other. A signal detection circuit 1390 (FIG. 10)obtains the difference between Vs and VD, and outputs a photosignal Vp,from which the noise component VD, due to fluctuation, is removed.

The overall structure of a photoelectric conversion apparatus of thissecond example embodiment, except as discussed above, is the same asthat of the photoelectric conversion apparatus 1200 of the firstembodiment shown in FIG. 5, and a separate figure and detailedexplanation is therefore omitted.

Operation of the photoelectric conversion device 130 will be explainedwith reference to the timing chart shown in FIG. 11. This timing chartrepresents the case where the intensity of the incident light issubstantially the same over successive detection cycles. Again, only asingle cycle of operation from t10 to t20 of the photoelectricconversion device 130 will be explained for purposes of simplification.

Before t10 the shutter 1200C has been in the closed state based on thecontrol signal SH supplied from the controller 1200D. Also, before t10,the driving pulse φTG is at a high level, the driving pulse φRSD is at alow level, the driving pulse φRSG is at a high level, and the drivingpulse φRST is at a low level. The electric signal Vout (that is, thepotential difference between the two ends of the capacitor C1) occurringat the node N1 has a value Vs corresponding to the incident light of theprevious cycle.

At t10, the driving pulse φRSG is inverted to the low level, and theP-type reset transistor QRSG is turned on. At the same time, the drivingpulse φRSD reaches an intermediate level VGM, and the voltage VGM isapplied to the turned-on reset transistor QRSG.

Also at t10, the driving pulse φRST becomes high, and the resettransistor QRST is turned on, whereby the charge accumulated in thecapacitor C1 is removed. At this time, the electric signal Voutoccurring at the node N1 becomes the ground level. In other words, thecapacitor C1 is reset.

At t11, the control signal SH becomes low, and the shutter 1200C isopened, whereby exposure starts.

Also at t11, the driving pulse φRSG returns to the high level, and thereset transistor QRSG is turned off. The driving pulse φRSD also returnsto the low level.) In addition, the driving pulse φRST returns to thelow level, and the reset transistor QRST is also turned off.

Thus, even after the exposure time starts, the driving pulse φTG remainsat the high level, and the transfer transistor QTG is still in the OFFstate. Accordingly, the signal charge generated in the photodiode 131upon the start of the exposure time is accumulated in the photodiode131, and it is not supplied to the gate region 132A of the JFET.

Because the shutter 1200C is opened at t11, the gate region 132A alsogenerates a signal charge in response to the incident light, and theamount of the charge gradually increases over time.

In this charge-increasing process, when the potential difference betweenthe gate and the source of the JFET exceeds a threshold value (at t12),the JFET is turned on.

If the charge accumulated in the gate region 132A of the JFET is Qj, thegate capacitance is Cj, and the gate potential of the JFET is Vjg, thenthe gate potential Vjg may be expressed as

    Vjg=V.sub.GM +Qj/Cj

where V_(GM) represents the voltage of φRSD at t10 shown in FIG. 11.

As the charge generated in the gate region 132A of the JFET increases,when the value of Vjg reaches or exceeds a threshold voltage Vj of theJFET (Vjg≧Vj), the value of the electric signal Vout starts increasing(after t12).

When the JFET is turned on at t12, electric current flows into thecapacitor C1 from the constant voltage source VDD via the JFET, wherebythe capacitor C1 starts being charged.

The charging of the capacitor C1 continues until the potentialdifference between the gate and the source of the JFET reaches the valuecorresponding to the signal charge accumulated in the gate region 132A.In other words, the potential difference between the two ends of thecapacitor C1 becomes the electric signal Vout, which corresponds to thesignal charge accumulated in the gate region 132A of the JFET.

Since the signal charge generated in the photodiode 131 has not yet beentransferred to the gate region 132A at the point in time t11, theelectric signal Vout takes on the value Vout2, which corresponds to thesignal charge generated in the gate region 132A.

This electric signal Vout2 is monitored in order to determine theexposure time. When Vout2 reaches the reference value Vref at t13, thecontrol signal SH is changed to the high level, and the shutter isclosed. (The exposure time ends.) Thus, the exposure time is from t11 tot13.

At t13, the driving pulse φRST is changed to the high level, and thecapacitor C1 is reset, that is, the charge accumulated in the capacitorC1 is removed. At the same time, the driving pulse φRSG becomes low,which causes the reset transistor QRSG to be turned on, and the drivingpulse φRSD reaches a peak (i.e., the readout level VGH), which causesthe gate region 132A of the JFET to be reset.

Upon the application of this constant voltage VGH (i.e., the readoutlevel) to the gate region 132A, the value of the electric signal Voutoccurring at the source (node N1) of the JFET becomes the referencesignal voltage VD, which corresponds to the dark output.

At t14, the driving pulse φRSD is again changed to the low level, andthe driving pulse φRSG is changed to the high level. The gate region132A of the JFET is thus put into a floating state, while the electricsignal Vout occurring at the source (node N1) remains at VD.

At this time, t14, the driving pulse φRST is changed to the low level,and the reset state of the capacitor C1 is terminated. Thus, thecapacitor C1 is prepared to be charged.

At t15, the driving pulse φTG is changed to the low level, and thetransfer transistor QTG is turned on, whereby the signal chargegenerated and accumulated in the photodiode during the period from t11to t12 is transferred to the gate region 132A of the JFET.

At this time, the value of the electric signal Vout occurring at thesource (node N1) of the JFET becomes Vs, which corresponds to the signalcharge generated and accumulated in the photodiode 131.

At t16, the driving pulse φTG is changed to the high level, the transfertransistor QTG is turned off, and the gate region 132A of the JFET isput into a floating state, while the value of the electric signal Voutoccurring at the node N1 remains at Vs, corresponding to the signalcharge generated in the photodiode 131.

At t20, the driving pulse φRSG becomes low, and the P-type resettransistor QRSG is turned on again. Also, the driving pulse φRSD againreaches the intermediate level (i.e., the constant voltage VGM), and thevoltage VGM is applied to the gate region 132A of the JFET. The drivingpulse φRST is changed to the high level (which causes the resettransistor QRST to be turned on), and the charge accumulated in thecapacitor C1 is removed. At this time, the electric signal at the source(node N1) of the JFET becomes ground level.

The operations from t10 through t20 are then repeated in the subsequentprocesses in order to perform successive cycles of light detection.

Both the electric signal VD obtained in the period t13 to t15 and theelectric signal Vs obtained in the period t15 to t20 are supplied to thesignal detection circuit 1390 shown in FIG. 10, and a photosignal Vprepresenting the difference of these two electric signals Vs and VD isfinally output.

Thus, in the photoelectric conversion apparatus according to the secondembodiment, the exposure time of the photoelectric conversion device 130(or more particularly, of the photodiode 131) is controlled based on thesignal charge generated by the gate region 132A, which represents thebrightness of the surroundings. In particular, the electric signalVout2, representing the signal charge generated by the gate region 132A,is compared with the reference value Vref, and the shutter opening timeis controlled based on the comparison result, whereby photography may beperformed with the optimal exposure time, even if the brightness of thesurroundings changes during the exposure.

A significant feature of this second example embodiment is that, unlikethe first embodiment, here the JFET of the photoelectric conversiondevice 130 does not have to be kept in the ON state. The JFET is turnedon only when the signal charge accumulated in the gate region 132Aexceeds a predetermined value. In addition, the capacitor C1 is chargedby an amount corresponding to the amount of signal charge generated inthe gate region 132A and, consequently, the power consumption can bereduced, as compared with the photoelectric conversion device 120 of thefirst embodiment.

Photoelectric Conversion Device Example Embodiment 3

Next, a photoelectric conversion device 140 and a photoelectricconversion apparatus 1400 according to a third example embodiment of theinvention will be described with reference to FIGS. 12-17. Featurescorresponding to those described in the embodiments above are shown withsimilar reference characters, but with a "4" for the first digit. Whereno additional description is given, the above description applies tocorresponding features.

In this embodiment, the photoelectric conversion device 140 is designedso that light strikes the gate region (i.e., control electrode) 142A ofthe JFET 142 and one of the main electrodes (i.e., the reset drain 144B)of the reset transistor 144, as well as the photodiode 141. Signalcharges generated in both the gate region 142A and the reset drain 144Bin response to the incident light are output.

The signal charges generated by the gate region 142A and the reset drain144B are compared with the reference value Vref, and the controller1400D (FIG. 16), which receives the comparison result, controls theopen-time of the shutter 1400C (i.e., the exposure time).

As shown in FIGS. 12 through 14, the photoelectric conversion device 140comprises a photodiode (i.e., a photoelectric conversion element) 141for generating a signal charge corresponding to incident light; anamplification transistor (JFET) 142 for outputting an electric signal(Vout) supplied to its gate region 142A; a P-type transfer transistor143 for supplying or transferring the signal charge generated andaccumulated in the photodiode 141 to the gate region 142A; and a P-typereset transistor 144 for removing the signal charge supplied to the gateregion 142A.

A light-blocking aluminum layer that typically covers the area of thephotoelectric conversion device except for the photodiode 141, isremoved from above the gate region 142A and the reset drain 144B, inorder to allow these regions to generate signal charges corresponding tothe incident light. The absence of any light-blocking aluminum layerabove these regions may be seen, for example in FIGS. 13 and 14.

The signal charge generated by the gate region 142A and the signalcharge generated by the reset drain 144B are combined. The combinedcharge is supplied to the photocurrent integrator 1470 (FIG. 15), whichproduces a corresponding output in the form of an amplified electricsignal Vip. This process will be described in more detail below.

The electric signal Vip corresponding to the sum of the signal chargesgenerated by the gate region 142A and the reset drain 144B is comparedwith the reference value Vref. The open-time of the shutter 1400C (i.e.,the exposure time) of the photoelectric conversion apparatus 1400 isdetermined based on the comparison result.

As for the structure of the photoelectric conversion device 140, theshape of the reset drain interconnection 1448 differs from itscounterpart in the photoelectric conversion device 120 of the firstexample embodiment shown in FIGS. 1 through 3.

In the photoelectric conversion device 120, the reset draininterconnection 1248 is formed so as to cover the light-receivingsurface of the reset drain 124B for the purpose of blocking light. Incontrast, in this third example embodiment, the reset draininterconnection 1448 is narrowed above the reset drain 144B in order toallow the incident light to strike the reset drain 144B. Thus, thephotoelectric conversion device 140 is designed so that the photodiode141, the gate region 142A, and the reset drain 144B, all of which aresemiconductor regions, generate signal charges in response to incidentlight.

The rest of the structures of the photoelectric conversion device 140,including the JFET 142, the transfer transistor 143, and the resettransistor 144, are the same as their counterparts with similarreference characters in the photoelectric conversion device 120 of thefirst embodiment, and detailed explanation of them will therefore beomitted.

As shown in FIGS. 12 through 14, the photoelectric conversion device 140also includes a transfer gate 143C, a reset gate 144C, a color filter145, a vertical signal line 1428, a transfer gate interconnection 1431,a reset gate interconnection 1447, and a reset drain interconnection1448.

FIG. 15 shows the circuit structure of the photoelectric conversiondevice 140 and the signal detection circuit 1490 connected to thephotoelectric conversion device 140. FIG. 16 shows the structure of aphotoelectric conversion apparatus 1400 using the photoelectricconversion device 140 as the light-receiving device 1400B, the operationof which is shown in the timing chart of FIG. 17.

As shown in FIG. 15, one of the main electrodes (i.e., the reset drain144B) of the reset transistor QRSG is connected to the photocurrentintegrator 1470. This feature is different from the circuit structure ofthe photoelectric conversion device 120 of the first example embodiment.

This photocurrent integrator 1470 will now be explained in more detail.

The photocurrent integrator 1470 comprises two P-type MOS transistorsQPD1 and QPD2 connected in parallel to the reset drain 144B of the resettransistor QRSG, an N-type MOS second reset transistor QRST, a capacitorCL, and an inverting amplifier AP. The N-type MOS transistor QRST, thecapacitor CL, and the inverting amplifier AP are connected in parallelbetween the drain of the P-type MOS transistor QPD2 and the outputterminal OUT.

When signal charges generated by the gate region 142A and the resetdrain 144B are input to the photocurrent integrator 1470, these signalcharges are integrated by the actions of the inverting amplifier AP andthe capacitor CL, and the value corresponding to the integral resultoccurs as the potential difference (Vip) between the two ends of thecapacitor CL. The reset transistor QRST resets the capacitor CL toremove the potential difference which has accumulated in the capacitorCL.

During operation of the photoelectric conversion device 140 connected tothis photocurrent integrator 1470, an electric signal Vout, whichcorresponds to the signal charge generated by the photodiode 141, occursat the source of the JFET 142 due to its source-follower action and, atthe same time, an electric signal (i.e., a voltage) Vip, whichrepresents the integral value of the signal charges generated by thegate region 142A and the reset drain 144B, occurs at the output terminalOUT of the photocurrent integrator 1470.

As in the photoelectric conversion apparatus 1200 of the firstembodiment, a signal detection circuit 1490 is connected to the node N1,at which the electric signal Vout occurs. This signal Vout generated bythe source-follower action of the JFET 142 is compared with the electricsignal VD representing the dark output, and a photosignal Vp, from whichthe noise component VD due to fluctuation is removed, is produced. Thephotosignal Vp takes on a value corresponding to the intensity of theincident light on the photodiode 141. A sample-and-hold circuit 1491 anda difference calculation circuit 1492 are included in the signaldetection circuit 1490.

FIG. 16 is a block diagram showing the overall structure of thephotoelectric conversion apparatus 1400 using the photoelectricconversion device 140.

In the photoelectric conversion apparatus 1400 of the third embodiment,a light-receiving device 1400B, which comprises the photoelectricconversion device 140 and a driving circuit (not shown), outputs twoelectric signals Vout and Vip. While Vout is supplied to the signaldetection circuit 1490, Vip is supplied to the comparator 1480, whichdiffers from the way the photoelectric conversion apparatus 1200 of thefirst example embodiment functions.

With the photoelectric conversion apparatus 1400, a photosignal Vp isgenerated by the signal detection circuit 1490 by subtracting thereference signal voltage VD corresponding to the dark output from theelectric signal Vout corresponding to the signal charge generated by thephotodiode 141.

A control signal SH for controlling the opening time (i.e., the exposuretime) of the shutter 1400C built into the dark box 1400A is suppliedfrom the controller 1400D based on whether or not the electric signalVip, which corresponds to the signal charges generated by the gateregion 142A and the reset drain 144B, is smaller than the referencevalue Vref.

Next, a cycle of the light detection operation of the photoelectricconversion device 140 will be explained using the timing chart of FIG.17, which shows the driving pulses used in the case where the intensityof the incident light is substantially constant over multiple cycles.For ease of explanation, a single cycle of operation from t10 to t20will be explained.

Before t10, the shutter 1400C has been in the closed state based on thecontrol signal SH supplied from the controller 1400D, the driving pulseφTG is at a high level, the driving pulse φRSD is at a low level, andthe driving pulse φRSG is at a high level. In addition, the drivingpulses φPD1, φPD2, and φRST are at high levels.

Before t10, the value of the electric signal Vout at the node N1 is Vs,corresponding to the incident light of the previous cycle, and theelectric signal Vip occurring at the output terminal OUT of thephotocurrent integrator 1470 is at a predetermined level (that is, inthe reset state) because the reset transistor QRST is in the ON statewith the driving pulse φRST at the high level. Also at this time, boththe MOS transistors QPD1 and QPD2 are in the OFF state (with the drivingpulses φPD1 and φPD2 high).

At t10, the driving pulse φRSG is changed to the low level, and theP-type reset transistor QRSG is turned on. The driving pulse φPD1 alsobecomes low, and the MOS transistor QPD1 is turned on. Also, the drivingpulse φRSD reaches the readout level (i.e., the constant voltage VGH),and this constant voltage VGH is applied to the gate region 142A of theJFET 142 via the turned-on MOS transistor QPD1 and the reset transistorQRSG.

Upon the application of the constant voltage VGH to the gate region 142Aof the JFET 142, the electric signal Vout occurring at the node N1becomes the reference signal voltage VD, which corresponds to the darkoutput.

At t11, the control signal SH supplied from the controller 1400D becomeslow, and the shutter 1400C is opened, whereby exposure starts. At thistime, the driving pulse φPD1 returns to the high level, and the MOStransistor QPD1 is turned off. The driving pulse φRSD also returns tothe low level.

Because the shutter 1400C is opened at t11, not only the photodiode 141,but also the gate region 142A and the reset drain 144B start generatingsignal charges in response to incident light. Since the MOS transistorQPD1 is in the OFF state, the voltage of the driving pulse φRSD is notapplied to the reset drain 144B via the MOS transistor QPD1.

Also at t11, the driving pulse φRST is changed to the low level, and thereset state of the photocurrent integrator 1470 is ended. The drivingpulse φPD2 also becomes low, and the MOS transistor QPD2 is turned on,which allows the photocurrent integrator 1470 to receive a signal chargefrom the reset drain 144B.

Beginning at t11, the signal charges generated by the gate region 142Aand the reset drain 144B are supplied to the capacitor CL via theturned-on reset transistor QRSG and the turned-on MOS transistor QPD2,and an electric signal Vip corresponding to the potential differencebetween the two ends of the capacitor CL is produced at the outputterminal OUT.

The value of the electric signal Vip occurring at the output terminalOUT gradually decreases during the time t11 to t12 when the shutter1400C is open (that is, during the time when light is incident on thegate region 142A and the reset drain 144B).

The value of the electric signal Vip is compared with the referencevalue Vref by the comparator 1480 shown in FIG. 16. When the value ofthe electric signal Vip becomes equal to or less than Vref (at t12), thecontrol signal SH supplied from the controller 1400D to the shutter1400C is changed to the high level, and the shutter 1400C is closed.Thus, the exposure time is between t11 and t12.

The photodiode 141 generates and accumulates a signal charge in responseto the incident light over the course of the exposure time.

When the electric signal Vip corresponding to the signal chargegenerated by the gate region 142A and the reset drain 144B reaches thereference value Vref, and when the shutter 1400C is closed based on thecontrol signal SH being raised to the high level at t12, the drivingpulse φRSD is raised to the high level (that is, to the constant voltageVGH).

Also at t12, the driving pulse φPD1 becomes low, which causes the MOStransistor QPD1 to be turned on, and the voltage of the reset drain 144Band the voltage of the gate region 142A become the constant voltage VGHof the driving pulse RSD via the turned-on MOS transistor QPD1. Thus thegate region 142A is reset.

Additionally at t12, the driving pulse φPD2 becomes high, which causesthe MOS transistor QPD2 to be turned off, and the reset drain 144B isdisconnected from the photocurrent integrator 1470. At this time, thedriving pulse φRST is also raised to the ON (high) level, and thephotocurrent integrator 1470 is reset. Also at this time, the electricsignal Vip occurring at the output terminal OUT becomes the reset level,and the electric signal Vout occurring at the source 142B of the JFET142 remains at the reference signal voltage VD corresponding to the darkoutput.

During the period from t11 to t12, the driving pulse φTG is kept at thehigh level, and the transfer transistor QTG is kept in the OFF state.Therefore, the signal charge which began to be generated at thephotodiode 141 at the start of the exposure time is accumulated in thecharge accumulation region (i.e., the P-type impurity diffusion layer1412), and it is not transferred to the gate region 142A of the JFET142.

At t13, the driving pulse φRSD is again changed to the low level, thedriving pulse φRSG is changed to the high level, and the MOS transistorQPD1 is turned off with the driving pulse φPD1 going high.

The gate region 142A of the JFET 142 is thus put into a floating state,while the electric signal Vout occurring at the source (node N1) remainsat VD.

At t14, the driving pulse φTG is changed to the low level, and thetransfer transistor QTG is turned on.

Upon turning on the transfer transistor QTG, the signal charge generatedand accumulated in the photodiode 141 during the period from t11 to t12is transferred to the gate region 142A of the JFET 142.

Since the gate region 142A has been reset (and the shutter 1400 has beenclosed) before t14, the value of the electric signal Vout occurring atthe source 142B (node N1) of the JFET 142 becomes Vs, which correspondsto the signal charge generated and accumulated in the photodiode 141.

At t15, the driving pulse φTG is again changed to the high level, thetransfer transistor QTG is turned off, and the gate region 142A of theJFET 142 is put into a floating state, while the value of the electricsignal Vout occurring at the node N1 remains at Vs, corresponding to thesignal charge generated in the photodiode 141.

At t20, the driving pulse φRSD is raised to the readout level (i.e., theconstant voltage VGH), and the driving pulses φRSG and φPD1 are changedfrom the high level to the low level.

Upon the change of the driving pulse φRSG to the low level, the P-typereset transistor QRSG is again turned on, while upon the change of thedriving pulse φPD1 to the low level, the MOS transistor QPD1 is againturned on. Then, the driving pulse φRSD at the readout level VGH isapplied to the drain of the reset transistor QRSG and the gate region142A via these transistors QRSG and QPD1. Thus the gate region 142A isreset. At this time, the electric signal Vout occurring at the node N1returns to the reference signal voltage VD corresponding to the darkoutput.

The operations from t10 through t20 are then repeated in the subsequentprocess in order to perform successive cycles of light detection.

Both the electric signal VD obtained in the period t10 to t14 and theelectric signal Vs obtained in the period t14 to t20 are supplied to thesignal detection circuit 1490 shown in FIG. 15, and a photosignal Vprepresenting the difference of these two electric signals Vs and VD isproduced.

Thus, with the photoelectric conversion device 140, the intensity of theincident light to the photodiode 141 is monitored using the electricsignal Vip which represents the sum of the signal charges generated bythe gate region 142A and the reset drain 144B. The value of Vipgradually decreases, and when Vip becomes equal to or less than Vref,the shutter 1400C is closed, so that the optimal exposure time isselected according to the brightness of the surroundings during theactual exposure time.

In this example embodiment, the photoelectric conversion device 140 isdesigned so that three semiconductor regions, namely, the photodiode141, the gate region 142A of the JFET 142, and the reset drain 144B,generate and accumulate signal charges in response to the incidentlight. A color filter (e.g., a blue filter) 145 is provided above thelight-receiving surface of the photodiode 141.

By providing the color filter 145 above the light-receiving surface ofthe photodiode 141, the color component defined by the color filter 145(i.e., the blue component in this example) is extracted from theincident light using the photoelectric conversion device 140.

Although in this embodiment the signal charges generated by the gateregion 142A and the reset drain 144B are used only to determine theexposure time, these signal charges can also be added to the signalcharge generated by the photodiode 141, as in the first modification ofthe first example embodiment above, so as to contribute to thephotosignal Vp output from the photoelectric conversion device 140.

In this case, another color filter having the same color as the colorfilter 145 may be provided above the light-receiving surfaces of thegate region 142A and the reset drain 144B.

With the color filters of the same color, the gate region 142A and thereset drain 144B detect the same light component as the photodiodedetects. Accordingly, by monitoring the intensity of this colorcomponent, the exposure time can be adjusted more accurately. Inaddition, by adding the signal charges generated in these regions 142Aand 144B to the signal charge generated by the photodiode 141, thephotoelectric conversion efficiency can be improved.

As an alternative, a color filter having a different color from thecolor filter 145 may be provided above the light-receiving surfaces ofthe gate region 142A of the JFET 142 and the reset drain 144B. Forinstance, a blue filter may be provided above the photodiode 141, and ared filter above the gate region 142A and the reset drain 144B.

With this arrangement (using color filters of different colors), thesame effect can be achieved as is achieved by the first embodiment.

That is, for example, when an object is illuminated with red light andradiates blue light in addition to red light in return, the intensityratio of red light to blue light may be detected. If the intensity ofthe radiated red light is strong, a blue filter is provided above thelight-receiving surface of the photodiode 141 which has a relativelylarge light-receiving area, and a red filter is provided above thelight-receiving surfaces of the gate region 142A of the JFET 142 and thereset drain 144B, whereby the intensity ratio of the red spectralcomponent detected by the gate region 142A and the reset drain 144B tothe blue spectral component detected by the photodiode 141 can bedetected with a high degree of accuracy.

As still another alternative, a color filter (for example, a red filter)may be provided only above the light-receiving surfaces of the gateregion 142A of the JFET 142 and the reset drain 144B, without providingany color filter above the light-receiving surface of the photodiode141.

In this case, the photodiode 141 detects the intensity of the incidentlight, which contains various color components, while the gate region142A and the reset drain 144B detect a specific color component of theincident light. The spectral characteristics (i.e., color information)of the incident light can be accurately obtained from the known spectralsensitivity of the detected light, based on the intensity of thespecific light component detected by the gate region 142A and the resetdrain 144B.

In this embodiment, the signal charges generated in the gate region 142Aand the reset drain 144B are integrated by the photocurrent integrator1470, and then the resultant signal is output from the output terminalOUT. However, if desired, the original signal charges may be outputwithout integrating them.

Photoelectric Conversion Device Example Embodiment 4

Next, a photoelectric conversion device 150 and a photoelectricconversion apparatus 1500 according to a fourth example embodiment ofthe invention will be described with reference to FIGS. 18-22. Featurescorresponding to features of previously described embodiments are givensimilar reference characters, but with a "5" for the first digit. Whereno specific description is given, the corresponding description aboveapplies.

As in the photoelectric conversion device 140 of the third embodiment,the photoelectric conversion device 150 is designed so that lightstrikes the gate region 152A and the reset drain 154B, as well as thephotodiode 151. However, unlike the third embodiment, an electric signalVout2 corresponding to the signal charge generated by the gate region152A is output from the source 152B of the JFET 152. An electric signalVip corresponding to the signal charge generated by the reset drain 154Bis output from the output terminal OUT of the photocurrent integrator1570.

The electric signal Vout2 corresponding to the signal charge generatedby the gate region 152A is compared with the reference value Vref1. Theelectric signal Vip corresponding to the signal charge generated by thereset drain 154B is compared with the reference value Vref2. If eitherVout2 or Vip exceeds its associated reference value, then the shutter1500C is closed.

FIGS. 18 through 20 illustrate the structure of the photoelectricconversion device 150 of this embodiment. Similar to the photoelectricconversion device 140 of the third embodiment, the photoelectricconversion device 150 comprises a photodiode 151 for generating a signalcharge corresponding to the incident light; an amplification transistor(JFET) 152 for outputting an electric signal (Vout) supplied to its gateregion 152A; a P-type transfer transistor 153 for supplying ortransferring the signal charge generated and accumulated in thephotodiode 151 to the gate region 152A; and a P-type reset transistor154 for removing the signal charge supplied to the gate region 152A.

As shown in FIGS. 19 and 20, no blocking film is provided at least abovethe gate region 152A of the JFET 152 and the reset drain 154B of thereset transistor 154, in order to allow the gate region 152A and thereset drain 154B to generate signal charges in response to the incidentlight.

The signal charge generated by the gate region 152A occurs as anelectric signal Vout directly at the source of the JFET 152. On theother hand, the signal charge generated by the reset drain 154B occursas an electric signal Vip at the output terminal OUT of the photocurrentintegrator 1570.

In this photoelectric conversion device 150, a color filter 155B isprovided above the photodiode 151, a color filter 155R is provided abovethe gate region 152A, and a color filter 155G is provided above thereset drain 154B. Only this part of the arrangement differs from thephotoelectric conversion device 140 of the third embodiment; the rest ofthe structure is the same.

FIG. 21 is a circuit diagram showing the photoelectric conversion device150 and the signal detection circuit 1590 connected to the photoelectricconversion device 150. FIG. 22 illustrates the photoelectric conversionapparatus 1500 using the photoelectric conversion device as alight-receiving device. FIGS. 23 and 24 are timing charts used forexplaining the operation of the photoelectric conversion device 150.

In the photoelectric conversion device 150 having the circuit structureshown in FIG. 21, the electric signal Vout1, corresponding to the signalcharge generated by the photodiode 151, and the electric signal Vout2,corresponding to the signal charge generated by the gate region 152A,occur at the source of the JFET 152 at different times because of thesource-follower action of the JFET 152. The electric signal Vipcorresponding to the signal charge generated by the reset drain 154Boccurs at the output terminal OUT of the photocurrent integrator 1570.The structure and the operation of the photocurrent integrator 1570 arethe same as those of the photocurrent integrator 1470 used in the thirdembodiment, and detailed explanation will therefore be omitted here.

FIG. 22 is a block diagram showing the overall structure of thephotoelectric apparatus 1500 using the photoelectric conversion device150 as a light-receiving device 1500B.

As shown in this figure, three signals Vout1, Vout2, and Vip are outputfrom the light-receiving device 1500B, which comprises the photoelectricconversion device 150 and a driving circuit (not shown). The electricsignal Vout1 is supplied to the signal detection circuit 1590, theelectric signal Vout2 is supplied to the comparator 1580A, and theelectric signal Vip is supplied to the comparator 1580B. Thisarrangement differs from the photoelectric apparatus 1400 of the thirdexample embodiment.

With this arrangement, the signal detection circuit 1590 subtracts thereference signal voltage VD, which corresponds to the dark output, fromthe electric signal Vout1, which corresponds to the signal chargegenerated by the photodiode 151. The signal detection circuit 1590outputs a resulting photosignal Vp.

The electric signal Vout2 corresponding to the signal charge generatedby the gate region 152A is compared with the reference value Vref1,while the electric signal Vip corresponding to the signal chargegenerated by the reset drain 154B is compared with the reference valueVref2. The controller 1500D outputs a control signal SH for controllingthe opening time (i.e., the exposure time) of the shutter 1500C builtinto the dark box 1500A based on the comparison results.

The light-detection operation of the photoelectric conversion device 150will now be explained using the timing chart of FIG. 23, which shows thedriving pulses used in the case where the intensity of the incidentlight is substantially constant over multiple cycles. For ease ofexplanation, a single cycle of operation from t10 to t20 will beexplained.

Before t10 the shutter 1500C has been in the closed state based on thecontrol signal SH supplied from the controller 1500D. The driving pulseφTG is at a high level, the driving pulse φRSD is at a low level, andthe driving pulse φRSG is at a high level. In addition, the drivingpulses φPD1, φPD2, and φRST are at high levels.

The value of the electric signal Vout occurring at the node N1 is Vs,corresponding to the incident light of the previous cycle, and theelectric signal Vip occurring at the output terminal OUT of thephotocurrent integrator 1570 is at ground level (that is, in the resetstate).

At t10, the driving pulse φRSG is changed to the low level, which causesthe P-type reset transistor QRSG to be turned on. The driving pulse φPD1also becomes low, which causes the MOS transistor QPD1 to be turned on.

The driving pulse φRSD reaches the readout level (i.e., the constantvoltage VGH). This constant voltage VGH is applied to the reset drain154B of the reset transistor QRSG via the turned-on MOS transistor QPD1.The potential of the reset drain 154B is further supplied to the gateregion 152A of the JFET 152.

At t11, the control signal SH supplied from the controller 1500D becomeslow, and the shutter 1500C is opened, whereby exposure starts. Upon theopening of the shutter 1500C, the gate region 152A and the reset drain154B, as well as the photodiode 151, start generating signal charges inresponse to incident light.

Also at t11, the driving pulse φRSD is changed to the low level, thedriving pulse φRSG is changed to the high level, the driving pulse φPD1is changed to the high level, the driving pulse φPD2 is changed to thelow level, and the driving pulse φRST is changed to the low level.

Upon the change of the driving pulse φRSG to the high level, the resettransistor QRSG is turned off. Consequently, the signal charge generatedby the gate region 152A of the JFET 154 is accumulated in this gateregion 152A alone, and the electric signal Vout2 occurring at the sourceof the JFET 152 takes on a value corresponding to this signal charge.The value of the electric signal Vout2 gradually increases during thetime when the shutter 1500C is open (t11 to t12).

In addition, at t11, the change of the driving pulse φRST to the lowlevel terminates the reset state of the photocurrent integrator 1570.The change of the driving pulse φPD2 to the low level causes the MOStransistor QPD2 to be turned on, whereby the signal charge generated bythe reset drain 154B starts being integrated by the photocurrentintegrator 1570.

Thus, beginning at t11, the signal charge generated by the reset drain154B is integrated by the photocurrent integrator 1570 via the turned-onMOS transistor QPD2, and the electric signal Vip corresponding to theintegral value occurs at the output terminal OUT. At this time, the MOStransistor QPD1 is in the OFF state with the driving pulse φPD1 at thehigh level.

The value of the electric signal Vip occurring at the output terminalOUT gradually decreases during the time when the shutter 1500C is open(t11 to t12).

The gradually varying electric signals Vout2 and Vip are compared withthe reference values Vref1 and Vref2, respectively, by the comparators1580A and 1580B shown in FIG. 22. When either Vout2 or Vip exceeds itsassociated reference value (Vref1 or Vref2), the comparison result issupplied to the controller 1500D. The timing chart of FIG. 23 shows thecase in which the electric signal Vout2 exceeds the reference valueVref1, and the timing chart of FIG. 24 shows the case in which theelectric signal Vip exceeds the reference value Vref2.

Upon receiving the comparison result, the controller 1500D changes thecontrol signal SH to the high level in order to close the shutter 1500C.The exposure time thus ends.

At t12, at which time either Vout2 or Vip exceeds the associatedreference value Vref1 or Vref2, the driving pulse φRSD is raised to thereadout level VGH, and the driving pulses φRSG and φPD1 are changed tothe low level.

The change of the driving pulse φPD1 to the low level causes the MOStransistor QPD1 to be turned on. The change of the driving pulse φRSG tothe low level causes the reset transistor QRSG to be turned on.

The readout voltage VGH is supplied to the reset drain 154B via theturned-on MOS transistor QPD1. The readout voltage VGH is furthersupplied to the gate region 152A of the JFET 152 via the turned-on MOStransistor QPD1 and the reset transistor QRSG, whereby the gate region152A is reset.

The voltage VGH supplied to the gate region 152A causes the electricsignal Vout occurring at the source of the JFET 152 to reach thereference signal voltage VD, which corresponds to the dark output.

In addition, the change of the driving pulse φPD2 to the high levelcauses the MOS transistor QPD2 to be turned off. At this time, thedriving pulse φRST is changed to the high level, and the photocurrentintegrator 1570 is reset.

During the period from t11 to t12, the driving pulse φTG is kept at thehigh level, and the transfer transistor QTG is kept in the OFF state.Therefore, the signal charge which begins accumulating in the photodiode151 at the start of the exposure time is accumulated in photodiode 151alone, without being transferred to the gate region 152A of the JFET152.

At t13, the driving pulse φRSD is again changed to the low level, andthe driving pulse φRSG is changed to the high level. At this time, thegate region 152A of the JFET 152 is put into a floating state, while theelectric signal Vout at the source (node N1) remains at VD.

At t14, the driving pulse φTG is changed to the low level, and thetransfer transistor QTG is turned on.

Upon turning on the transfer transistor QTG, the signal charge generatedand accumulated in the photodiode 151 during the period from t11 to t12is transferred to the gate region 152A of the JFET 152. Because the gateregion 152A has already been reset to the readout level, and because theshutter 1500C has already been closed before t14, the value of theelectric signal Vout occurring at the source (i.e., the node N1) of theJFET 152 becomes Vs, corresponding to the signal charge generated andaccumulated in the photodiode 151.

At t15, the driving pulse φTG is changed to the high level, the transfertransistor QTG is turned off, and the gate region 152A of the JFET 152is put into a floating state, while the value of the electric signalVout at the node N1 remains at Vs.

At t20, the driving pulses φRSG and φPD1 are changed from the high levelto the low level, and the driving pulse φRSD is raised to the high level(to VGH).

Upon the change of the driving pulse φRSG to the low level, the P-typereset transistor QRSG is again turned on. Upon the change of the drivingpulse φPD1 to the low level, the MOS transistor QPD1 is again turned on.The driving pulse φRSD at the readout level VGH is thus applied to thedrain of the reset transistor QRSG and the gate region 152A via theturned-on transistors QRSG and QPD1, whereby the gate region 152A isreset. At this time, the electric signal Vout at the node N1 returns tothe reference signal voltage VD corresponding to the dark output.

The operations from t10 through t20 are then repeated in order toperform successive cycles of light detection.

Both the electric signal VD obtained in the period t10 to t14 and theelectric signal Vs obtained in the period t14 to t20 are supplied to thesignal detection circuit 1590. A photosignal Vp representing thedifference of these two electric signals Vs and VD is produced.

Thus, with the photoelectric conversion device 150, the electric signalsVout2 and Vip, which correspond to the signal charges generated by thegate region 152A and the reset drain 154B, respectively, are comparedwith the reference values Vref1 and Vref2 by the comparators 1580A and1580B, respectively. The intensity of the incident light is monitoredbased on the comparison results in order to control the open-time of theshutter 1500C, whereby the optimal exposure time can be determined andemployed. In other words, the exposure time is controlled based on thesignal charges generated by the gate region 152A and the reset drain154B. Thus an object can be photographed with an exposure time that isoptimal in relative to the brightness of the surroundings, asrepresented by these signal charges.

In this fourth example embodiment, the photoelectric conversion device150 is designed so that three semiconductor regions, namely, thephotodiode 151, the gate region 152A of the JFET 152, and the resetdrain 154B, generate and accumulate signal charges in response toincident light. A blue filter 155B is provided above the light-receivingsurface of the photodiode 151, a red filter 155R is provided above thelight-receiving surface of the gate region 152A of the JFET 152, and agreen filter 155G is provided above the light-receiving surface of thereset drain 154B.

By providing the color filters 155B, 155R and 155G above thelight-receiving surfaces of the photodiode 151, the gate region 152A ofthe JFET 152, and the reset drain 154B, respectively, the spectralcharacteristics (i.e., the color information) of the incident light canbe obtained in more detail.

The photoelectric conversion device 150 using color filters of differentcolors has the same effect and advantages in measuring the properties ofan object as in the third example embodiment described above.

In the fourth embodiment, the signal charge generated by the reset drain154B is integrated by the photocurrent integrator 1570, and then it isoutput from its output terminal OUT. However, if desired, this signalcharge can be output without being integrated.

As has been described above, in the photoelectric conversion apparatusesusing the photodiodes 121, 131, 141, and 151 according to the firstthrough fourth example embodiments, the exposure time is determinedbased on the signal charges generated by the gate regions 122A, 132A,142A, and 152A and/or the signal charges generated by the reset drains144B and 154B, respectively. However, as an alternative, the time duringwhich the shutters 1200C, 1400C, and 1500C are held open (i.e., theexposure time) may be fixed in order to obtain color information basedon the signal charges generated by the gate regions 122A, 132A, 142A,and 152A, and/or the reset drains 144B and 154B during this fixedexposure time. In this case, the color information is added to theintensity information obtained from the light intensity detected by thephotodiodes 121, 131, 141, and 151, whereby more precise detection ofthe spectral components can be achieved.

Although, in the third and fourth embodiments, the signal chargesgenerated by the reset drains 144B and 154B in response to the incidentlight are output from the photocurrent integrator 1470 and 1570, thesesignal charges can also be transferred to the gate regions 142A and 152Aof the JFETs 142 and 152, respectively. In that case, electric signalscorresponding to these signal charges are output from the source (i.e.,the node N1) of the JFETs 142 and 152, respectively.

This arrangement can be achieved by turning on the reset transistorsQRSG (144 and 154) during the generation of the signal charges in thereset drains 144B and 154B in order to make the potentials of the resetdrains 144B and 154B equal to the potentials of the gate regions 142Aand 152A of the JFETs 142 and 152, respectively. As a result, electricsignals corresponding to the signal charges generated by the resetdrains 144B and 154B occur at the sources of the JFETs 142 and 152,respectively.

In this case, electric signals corresponding to the signal chargesgenerated by the gate regions 142A and 152A of the JFETs 142 and 152 maybe output from the sources of the JFETs 142 and 152 independently fromthe electric signals corresponding to the signal charges generated bythe reset drains 144B and 154B, or alternatively, the signal chargesgenerated by the gate regions 142A and 152A of the JFETs 142 and 152 maybe added to the signal charges generated by the reset drains 144B and154B, respectively, and electric signals representing the sum of thesesignal charges may be output from the sources (i.e., the nodes N1) ofthe JFETs 142 and 152. This can be achieved by appropriately adjustingthe high/low switching timing of the driving pulse φRSG supplied to thegates 144C and 154C of the reset transistors QRSG (144 and 154).

As another alternative, the electric signal corresponding to the signalcharge generated by the gate region 142A (or 152A in the fourthembodiment), and the electric signal corresponding to the signal chargegenerated by the reset drain 144B (or 154B), which are outputindependently of each other, may be added to or output separately fromthe electric signal corresponding to the signal charge generated by thephotodiode 121. In the former case, the sum is output from the source(i.e., the node N1) of the JFET 142 (or 152), while, in the latter case,the three independent electric signals are output from the source of theJFET 142 (or 152).

In the third and fourth embodiments, the photoelectric conversiondevices 140 and 150 are designed so that both the gate regions 142A and152A of the JFET 142 and 152, and the reset drains 144B and 154Bgenerate signal charges in response to the incident light. However, thegate regions 142A and 152A of the JFETs 142 and 152 may be covered, forexample, with the reset drain interconnection (e.g., aluminuminterconnection), so that only the reset drains 144B and 154B generatesignal charges.

In this case, the signal charges generated by the reset drains 144B and154B are transferred to the gate regions 142A and 152A of the JFETs 142and 152, respectively, and are output from the sources (i.e., the nodesN1) of the JFETs 142 and 152. Alternatively, they may be output from thedrain of the reset transistor QRSG (124).

Although, in the first through fourth embodiments, the structures andoperations of the photoelectric conversion devices 120, 130, 140, and150 were explained on the assumption that a single unit is used, aplurality of photoelectric conversion devices may be arranged in anarray in order to form an image sensor.

In the first, third and fourth embodiments, two-valued driving pulsesφRSD having a high level (i.e., the readout level VGH) and a low level,are supplied to the reset drains 124B, 144B and 154B of thephotoelectric conversion devices 120, 140 and 150. However, thephotoelectric conversion devices 120, 140, and 150 may be designed sothat constant level (i.e., high level VGH) signals are supplied to thereset drains 124B, 144B, and 154B.

In the second embodiment, a three-valued driving pulse φRSD having apeak (VGH), an intermediate level VGM, and a low level is supplied tothe reset drain of the photoelectric conversion device 130. However, thephotoelectric conversion device 130 may be configured so that atwo-valued driving pulse φRSD is supplied to the reset drain, as in thefirst embodiment. Alternatively, the photoelectric conversion device 130may be configured so that a constant level (VGH) signal is supplied tothe reset drain.

In the first through fourth embodiments, the time during which theshutter is held open (i.e., the exposure time) is controlled based onthe signal charge generated by the secondary light-receiving elements(i.e., the gate region and the reset drain). However, the signal chargesgenerated by these secondary light-receiving elements (i.e., the gateregion and the reset drain) may be simply output from the photoelectricconversion device when exposure-time control is not performed.

In the photoelectric conversion devices 120, 130, 140 and 150 accordingto the first through fourth embodiments of the invention, a transfertransistor is positioned between the photodiode, which is aphotoelectric conversion element, and the amplification transistor,which is an output unit. However, the invention also encompasses aphotoelectric conversion device having no transfer transistor, in whichthe photodiode and the control electrode of the amplification transistorare electrically connected directly to each other, or the photodiode andthe amplification transistor are integratedly formed as a single unit.In this case, the photodiode or the phototransistor is used as a primarylight-receiving element, and the reset drain of the reset transistor isused as a secondary light-receiving element.

As has been described above, the control electrode (gate) of theamplification transistor, in addition to the photoelectric conversionelement, can generate a signal charge in response to incident light. Thetotal light-receiving area of the photoelectric conversion device isthus substantially increased, and the photoelectric conversion rate ofeach pixel is improved.

A light component having a specific wavelength can be efficientlydetected based on the spectral component of the incident light. Thecolor information of the incident light can also be detected precisely.

Because the brightness of the surroundings of the photoelectricconversion apparatus is monitored based on the signal charge generatedby the control electrode, and because the exposure time is automaticallyadjusted based on the monitoring result, a clear image can always beobtained.

One of the main electrodes of the reset transistor can also generate asignal charge in response to the incident light, in addition to thephotoelectric conversion element. Consequently, the totallight-receiving area of the photoelectric conversion device can beincreased, and the photoelectric conversion rate of each pixel can beimproved.

Furthermore, both the control electrode of the amplification transistorand one of the main electrodes of the reset transistor can generatesignal charges in response to the incident light, in addition to thephotoelectric conversion element. Consequently, the totallight-receiving area of the photoelectric conversion device can beincreased, and the photoelectric conversion rate of each pixel can beimproved.

The photoelectric conversion devices of the present invention areparticularly useful as pixels in an image sensor array, and particularlyas pixels in a fixed-image image sensor array, such as useful in digitalphotography. In such an array, not every pixel need be of the inventivetype, i.e., not every pixel need have multiple light-sensitive elementsin order to provide the important advantage of directly monitoringexposure light during the exposure. Fourteen example pixel forms usefulin such a fixed-image image sensor array are described below,particularly in terms of their differences from known pixels for use insuch arrays as described above with reference to FIGS. 54 and 55. Bothpixels with multiple light sensitive elements and pixels with singlelight sensitive elements are described.

Pixel 1

FIG. 25 shows a first pixel example. FIG. 25(a) is a plan view, FIG.25(b) is a cross-sectional view taken along the X1-X2 line in FIG.25(a), and FIG. 25(c) is a cross-sectional view taken along the Y1-Y2line in FIG. 25(a). FIG. 26(a) is a circuit diagram showing theequivalent circuits of this first pixel.

In FIG. 25 and FIG. 26(a), identical or corresponding elements in FIGS.54 and 55 are assigned the same reference characters. Note thatleft-right orientation of FIG. 25(a) and 25(b) is reversed from that ofFIG. 26(a).

This first pixel differs from the pixel shown in FIG. 54 in thefollowing respects.

In the pixel shown in FIG. 54, reset drain interconnect 24, which alsofunctions as a light shielding film, also shields light from the resetdrain 4 area. However, in this first pixel, aperture 24a is formed onthe area of reset drain 4 where reset drain interconnect 24 is located,making it possible for a portion of reset drain 4 to receive incominglight. Reset drain 4 is a P-type semiconductor area, with an N-typesemiconductor area 11 (of opposite conductivity) below. Since resetdrain 4 and N-type semiconductor area 11 are constantly in inverse bias(VDD>φRSD), the reset drain 4 in this first pixel functions asphotodiode 40, separately from the photodiode 1 that serves as thephotoelectric conversion element. This photodiode 40 generatesphotoelectric current in the form of signal charges (in this example,holes) generated in proportion to the light entering aperture 24a. Inother words, in pixel 1, the exposed area of reset drain 4 generates asignal charge proportional to the incoming light.

As an additional difference, in the pixel shown in FIG. 54, reset drain4 (P-type semiconductor area) is directly connected electrically toreset drain interconnect 24 via contact 30, relay 23, and relay contact31. However, in the first pixel, these are removed, and reset drain 4 isnot directly connected electrically to reset drain interconnect 24.Removing relay 23, etc., from the first pixel increases the apertureratio of said photodiode 40.

Furthermore, in the pixel shown in FIG. 54, reset drain 4 and JFET 2gate 15 serve respectively as primary electrode areas for one another,together forming part of a P-channel MOSFET 9, a reset transistor forwhich reset gate electrode 5 serves as a control electrode. There is noswitching element between the adjacent pixels on either side in the rowdirection (in the horizontal scan direction, left-to-right in thefigure). In other words, there is no inter-pixel switching element.

In contrast, the first pixel is equipped with gate electrodes 5a on bothsides of the pixel (left and right in the figures), in addition to resetgate electrode 5 near the center of the pixel. The gate electrode 5a onthe left in FIGS. 25(a) and 25(b) is located in the boundary areabetween P-type gate area 15 of the pixel and a reset drain 4 of anadjacent pixel in the row direction (to the left in the figures). Thegate electrode 5a on the right in FIGS. 25(a) and 25(b) is located inthe boundary area between reset drain 4 of the pixel and a P-type gatearea 15 of an adjacent pixel in the row direction (to the right in thefigures). The gate electrodes 5a are formed of polysilicon and areseparated from the underlying semiconductor material by a layer of aninsulating material 33, as is reset gate electrode 5. Gate electrodes 5aand reset gate 5 are connected in common by a reset gate interconnection21.

The first pixel does not have the high-density N-type drain area 16 thatfunctions as a pixel separator area in the pixel of FIG. 54. Thecorresponding area, is left as N-type semiconductor in the form ofN-type semiconductor area 11.

Pixel 2

FIG. 26(b), which is a circuit diagram of the equivalent circuits in asecond example pixel useful with image sensor arrays of the presentinvention.

This second pixel is fundamentally the same as the first pixel shown inFIGS. 25(a)-25(c) and 26(a). It has the capability not only of obtainingimage signals but also of monitoring the quantity of light duringexposure. The only differences between this second pixel and the firstpixel are that inter-pixel gate electrode 5a on the left side in FIGS.25(a) and 25(b) is removed, so that it lacks the P-channel MOSFET 9a onthe left side in FIGS. 25(a) and 25(b). (Note that left-rightorientation of FIG. 25(a) and 25(b) is reversed from that of FIG.26(b).)

Pixel 3

FIG. 26(c) is a circuit diagram of the equivalent circuits of a thirdexample pixel useful in image sensors of the present invention.

This third pixel is fundamentally the same as the first pixel shown inFIGS. 25(a)-25(c) and 26(a). It has the capability not only of obtainingimage signals but also of monitoring the quantity of light duringexposure. The only differences between this third pixel and the firstpixel is that the inter-pixel gate electrode 5a shown on the right sidein FIGS. 25(a) and 25(b) is not present in the third pixel, and it thuslacks the P-channel MOSFET 9a on the right side in FIGS. 25(a) and25(b). (Note that the left-right orientation of FIGS. 25(a) and 25(b) isreversed from that of FIG. 26(c).)

Pixel 4

FIG. 27 illustrates a fourth example pixel useful in the context of thepresent invention. FIG. 27(a) is a plan view, FIG. 27(b) is across-sectional taken along the X3-X4 line in FIG. 27(a), and FIG. 27(c)is cross-sectional view taken along the Y3-Y4 line in FIG. 27(a). FIG.28(a) is a circuit diagram which shows an equivalent circuit for thisfourth pixel. In FIGS. 27(a)-27(c) and 28(a), the items identical orcorresponding to items in FIGS. 25 and 26 are assigned the samereference characters, and the corresponding description will not beduplicated. Note that left-right orientation of FIGS. 27(a) and 27(b) isreversed from that of FIG. 28(a).

This fourth pixel lacks the capability of monitoring the quantity oflight during exposure, but the element structure is fundamentally thesame as the first pixel shown in FIGS. 25 and 26(a). The onlydifferences between this fourth pixel and said first pixel are first,that there is no aperture 24a in the reset drain interconnection 24 inthe area where reset drain 4 is located. Light is thus shielded fromreset drain 4 by reset drain interconnection 24. Second, reset drain 4is directly connected electrically to reset drain interconnect 24 bycontact hole 30, relay 23, and relay contact 31.

Pixel 5

FIG. 28(b) is a circuit diagram showing the equivalent circuit of afifth example pixel useful in connection with the present invention.

This fifth pixel is fundamentally the same as the fourth pixel shown inFIGS. 27 and 28(a), and has no capability of monitoring the quantity oflight during exposure. The only differences between this fifth pixel andsaid fourth pixel are that inter-pixel gate electrode 5a on the lefthand side of FIGS. 27(a) and 27(b) is removed in this fifth pixel, suchthat there is no P-channel MOSFET 9a on the left of FIGS. 27(a) and27(b). Note that the left-right orientation of FIGS. 27(a) and 27(b) isreversed from that of FIG. 28(b).

Pixel 6

FIG. 28(c) is a circuit diagram of the equivalent circuit of a sixthexample pixel useful in the context of the present invention.

This sixth pixel is fundamentally the same as the fourth pixel shown inFIGS. 27(a)-27(c) and 28(a), and has no capability of monitoring thequantity of light during exposure. The only differences between thissixth pixel and the fourth pixel are that inter-pixel gate electrode 5aon the right hand side of FIGS. 27(a) and 27(b) is not present in thissixth pixel, meaning that there is no P-channel MOSFET 9a on the rightside of the pixel as in FIGS. 27(a) and 27(b). Note that left-rightorientation of FIGS. 27(a) and 27(b) is reversed from that of FIG.28(c).

Pixel 7

FIG. 28(d) is a circuit diagram showing an equivalent circuit of aseventh example pixel useful in the context of the present invention.

This seventh pixel is fundamentally the same as the fourth pixel shownin said FIGS. 27 and 28(a), and has no capability of monitoring thequantity of light during exposure. The only differences between thisseventh pixel and said fourth pixel are that the inter-pixel gateelectrodes 5a on both sides of FIGS. 27(a) and 27(b) are not present inthe seventh pixel, and there is thus no P-channel MOSFET 9a on eitherside of the pixel. This seventh pixel is thus essentially identical tothe pixel shown in FIG. 54. Note that left-right orientation of FIGS.27(a) and 27(b) is reversed from that of FIG. 28(d).

Pixel 8

FIG. 29 shows an eighth example pixel useful with the present invention.FIG. 29(a) is a plan view, FIG. 29(b) is a cross-sectional view takenalong the X5-X6 line in FIG. 29(a), and FIG. 29(c) is a cross-sectionalview taken along the Y5-Y6 line in FIG. 29(a). FIG. 30(a) is a circuitdiagram of an equivalent circuit of this eighth pixel. In FIG. 29 andFIG. 30(a), elements identical or corresponding to elements in FIG. 25and FIG. 26 are assigned the same reference characters, description ofwhich is not duplicated. Note that the left-right orientation of FIGS.29(a) and 29(b) is opposite that of FIG. 30(a).

This eighth pixel has the capability of monitoring the quantity of lightduring exposure, and the fundamental structure is the same as the firstpixel shown in FIGS. 25(a)-25(c) and 26(a). The differences between thiseighth pixel and the first pixel are that relay 23, reset draininterconnect 24, via contact hole 30, and relay contact 31 are presentover reset drain 4. Aperture 24a' is formed over the portion of resetdrain 4 where reset drain interconnect 24 is located, and it is formedso that a portion of the reset drain 4 can receive incoming light.However, as shown in FIGS. 29(a) and 29(b), this aperture 24a' differsfrom aperture 24a on said first pixel in that reset drain interconnect24 is partially left in place on sections of reset drain, 4 so thatrelay 23 and reset drain interconnect 24 are connected. In this eighthpixel, the aperture ratio of the photodiode 40, which comprises theexposed portion of reset drain 4, is smaller than that of the firstpixel.

Unlike the first pixel, since a portion of the reset drain interconnect24 and the relay 23 remain in this eighth pixel, reset drain 4 isdirectly connected electrically to reset drain interconnect 24.

Pixel 9

FIG. 30(b) is a circuit diagram of the equivalent circuit of a ninthexample pixel useful in the context of the present invention.

This ninth pixel is fundamentally the same as the eighth pixel shown inFIGS. 29(a)-29(c) and 30(a), and it has the capability of monitoring thequantity of light during exposure. The only differences between theninth pixel and the eighth pixel are that the ninth pixel has nointer-pixel gate electrode 5a such as that shown on the left hand sideof FIGS. 29(a) and 29(b), and there is consequently no P-channel MOSFET9a in the ninth pixel, as found on the left of FIGS. 29(a) 29(b). Notethat the left-right orientation of FIGS. 29(a) and 29(b) is reversedfrom that of FIG. 30(b).

Pixel 10

FIG. 30(c) is a circuit diagram of the equivalent circuit of a tenthexample pixel useful in the context of the present invention.

This tenth pixel is fundamentally the same as the eighth pixel shown inFIGS. 29(a)-29(c) and FIG. 30(a), and it has the capability ofmonitoring the quantity of light during exposure. The only differencebetween this tenth pixel and the eighth pixel is that this tenth pixelhas no inter-pixel gate electrode on the right side of the pixel,corresponding to the inter-pixel gate electrode 5a on the right side ofFIGS. 29(a) and 29(b) in the eighth pixel, and there is thus noP-channel MOSFET 9a on the right of the tenth pixel as shown on theright of FIGS. 29(a) and 29(b) in the eighth pixel. Note that theleft-right orientation of FIGS. 29(a) and 29(b) is reversed from that ofFIG. 30(c).

Pixel 11

FIG. 30(d) is a circuit diagram of an equivalent circuit of an eleventhexample pixel useful in the context of the present invention.

This eleventh pixel is fundamentally the same as the eighth pixel shownin FIGS. 29(a)-29(c) and 30(a), and it has the capability of monitoringthe quantity of light during exposure. The only difference between thiseleventh pixel and the eighth pixel are that there are no inter-pixelgate electrodes on either side of the eleventh pixel corresponding tointer-pixel gate electrodes 5a on the left and right sides of FIGS.29(a) and 29(b), and thus there are no P-channel MOSFETs on either sideof the eleventh pixel corresponding to P-channel MOSFETs 9a on eitherside of FIGS. 29(a) and 29(b). Note that the left-right orientation ofFIGS. 29(a) and 29(b) is reversed from that of FIG. 30(d).

Pixel 12

FIGS. 31 and 32 show the structure of a twelfth example pixel useful inthe context of the present invention. FIG. 31(a) is a plan view, FIG.31(b) is a cross-sectional view taken along the X7-X8 line in FIG.31(a), and FIG. 31(c) is a cross-sectional view taken along the Y7-Y8line in FIG. 31(a). FIG. 32 is a cross-sectional view taken along theY9-Y10 line in FIG. 31(a). In FIGS. 31 and 32, elements identical orcorresponding to elements in FIGS. 25 and 26 are assigned the samereference characters, and the corresponding descriptions will not berepeated.

The twelfth pixel has the same light monitoring capability as the firstpixel shown in FIGS. 25 and 26(a), and it has the same fundamentalstructure as the first pixel.

The twelfth pixel differs from the first pixel in the following ways.

First, the substrate 10 of the first pixel is a P-type semiconductorsubstrate, whereas the substrate 10 of the twelfth pixel is an N-typesemiconductor substrate.

Second, the twelfth pixel has no drain interconnect corresponding todrain interconnect 25 shown in FIG. 25. In the twelfth pixel, thevertical signal line (JFET source interconnect) 22 is positioned in theplace occupied by drain interconnect 25 in the first pixel, increasingthe aperture ratio of the twelfth pixel relative to that of the firstpixel.

Third, the twelfth pixel is equipped with overflow control areas 6a toconvey excess charges generated by the photodiodes 1 to the reset drains4. Overflow control area 6a is composed of the P-type charge storagearea 12 in the photodiode 1 and a P-type semiconductor area formedwithin the semiconductor layer 11 in the boundary area with reset drain4. The overflow control areas 6a control overflow by conducting excesscharges generated in the photodiodes 1 to the adjacent reset drains 4.

A high-density N-type semiconductor area 16 (similar to N-type drainarea 16) is formed along the semiconductor surface above overflowcontrol area 6a. In other words, P-type charge storage area 12 inphotodiode 1, P-type overflow control area 6a, and reset drain 4 serverespectively as a source area, a channel area, and a drain area, whilehigh-density N-type semiconductor area 16 and N-type semiconductor layer11 serve as a gate area, effectively forming a P-channel JFET 200 (FIG.32). This P-channel JFET 200 is in cutoff mode (disconnected) when thephotodiode 1 is operating normally, but when strong light enters thephotodiode 1 and charge in excess of a certain amount (in this case, apositive charge from the generation of holes) is stored in P-type chargestorage area 12, P-channel JFET 200 turns on. In other words, P-channelJFET 200 is designed to turn on when the potential of P-type chargestorage area 12 rises above a certain level. Therefore, excess chargesgenerated by photodiodes 1 flow to reset drains 4 via overflow controlareas 6a. The excess charges are then conducted away via reset draininterconnect 24.

The high-density N-type semiconductor area 16 formed along thesemiconductor surface above overflow control area 6a (a continuation orextension of N-type drain area 16 of JFET 2 [see FIG. 31(c)]) is formedcontinuously along high-density N-type semiconductor area 13 ofphotodiode 1, which is formed along the surface of photodiode 1.Consequently, the vicinity of the semiconductor surface for the P-typecharge storage area 12 of photodiode 1, including the surrounding areas,is covered by high-density N-type semiconductor areas (13 and 16),making photodiode 1 a buried photodiode. There is no structurally formedhigh-density N-type semiconductor area (13 or 16) at the transfer gate 3of photodiode 1, but the photodiode is able to maintain its performanceas a buried photodiode. This is because during the time when photodiode1 is executing the signal charge storage operation by photoelectricconversion, the high-density N-type semiconductor area applies ahigh-level pulse voltage when transfer gate 3 is off, resulting ininduction of electrons into the semiconductor surface in the area oftransfer gate 3. Thus, photodiode 1 is a buried photodiode equipped witha JFET-type lateral overflow drain structure.

As is the case with a buried photodiode with a vertical overflowstructure, the overflow structure makes it possible to suppressblooming, smearing and other types of charge overflow phenomena. Also,because it is a buried photodiode, evacuated layers that occur in theP/N junction not reach the semiconductor surface, which suppresses darkcurrent. In addition, after the charges have been transferred, nocharges remain in the photodiodes (due to complete charge transfer orcomplete evacuation), as a result, the apparatus yields idealcharacteristics in terms of minimizing after-images and reset noise.

The equivalent circuits for this twelfth pixel are the same as theequivalent circuits for said first pixel, and are as shown in FIG.26(a).

Pixel 13

FIGS. 33 and 34 show a thirteenth example pixel useful in the context ofthe present invention. FIG. 33(a) is a plan view, FIG. 33(b) is across-sectional view taken along the X11-X12 line in FIG. 33(a), andFIG. 33(c) is a cross-sectional view taken along the Y11-Y12 line inFIG. 33(a). FIG. 34 is a cross-sectional view taken along the Y13-Y14line in FIG. 33(a). In FIGS. 33 and 34, elements identical orcorresponding to elements in FIGS. 25, 26, 31, and 32 are assigned thesame reference characters, and the description thereof will not berepeated.

This thirteenth pixel lacks light quantity monitoring capabilities, asdoes the fourth pixel shown in FIGS. 27 and 28. The fundamental elementstructure is the same as the fourth pixel of FIGS. 27 and 28(a).

The thirteenth pixel differs from said fourth pixel in same ways asthose in which the twelfth pixel differs from the first pixel. That is,whereas the fourth pixel utilizes a P-type semiconductor substrate assubstrate 10, an N-type semiconductor substrate is used as substrate 10in this thirteenth pixel. Also, this thirteenth pixel omits the draininterconnect 25 shown in FIG. 27, and vertical signal line (JFET 2source interconnect) 22 is put in place of drain interconnect 25.Furthermore, the thirteenth pixel is equipped with overflow controlareas 6a to conduct excess charges generated by photodiodes 1 to resetdrains 4.

The equivalent circuit for this thirteenth pixel is the same as theequivalent circuit for the fourth pixel as shown in FIG. 28(a).

Pixel 14

FIGS. 35 and 36 show a fourteenth example pixel useful in the context ofthe present invention. FIG. 35(a) is a plan view, FIG. 35(b) is across-sectional view taken along the X15-X16 line in FIG. 35(a), andFIG. 35(c) is a cross-sectional view taken along the Y15-Y16 line inFIG. 35(a). FIG. 36 is a cross-sectional view taken along the Y17-Y18line in FIG. 35(a). In FIGS. 35 and 36, elements identical orcorresponding to elements in FIGS. 25, 26, 31, and 32 are assigned thesame reference characters, and the description thereof will not berepeated.

This fourteenth pixel has the same light quantity monitoringcapabilities as the eighth pixel shown in FIGS. 29 and 30, and itsfundamental element structure is the same as that of the eighth pixel ofFIG. 30(a). The fourteenth pixel differs from the eighth pixel in thesame ways in which the twelfth pixel differs from the first pixel. Thatis, the eighth pixel utilizes a P-type semiconductor substrate assubstrate 10, whereas the fourteenth pixel uses an N-type semiconductorsubstrate as substrate 10. Also, the fourteenth pixel eliminates thedrain interconnect 25 shown in FIG. 29, and vertical signal line (JFET 2source interconnect) 22 is put in place of drain interconnect 25.Furthermore, the fourteenth pixel is equipped with overflow controlareas 6a to convey excess charges generated by photodiodes 1 to resetdrains 4.

The equivalent circuit of this fourteenth pixel is the same as theequivalent circuit for the eighth pixel shown in FIG. 30(a).

Other Pixels

Just as the first pixel is modified to obtain the second and thirdpixels, the fourth to obtain the fifth through seventh, and the eighthto obtain the ninth through eleventh, as described above, so too is itpossible to obtain a variety of pixels by similarly modifying thetwelfth, thirteenth, and fourteenth pixels.

Image Sensor Array Example Embodiment 1

FIG. 37 is a circuit diagram of an example embodiment of a fixed-imageimage sensor array for an image capture apparatus.

In this embodiment, the array comprises a two-dimensional matrix (m×n)of the first pixel as described above and shown in FIGS. 25 and 26(a),and of the fourth pixel as described above and shown in FIGS. 27 and28(a). At or near the center of the matrix is a two-dimensional matrix(k×1) of first pixels, surrounded by fourth pixels. In FIG. 37, thefirst pixels are shown enclosed in the dashed line.

In each matrix row of this embodiment, reset drain 4 and gate area 15 ofJFET 2 alternate in the row direction (the horizontal scan direction).Between each pixel is the gate electrode 5a forming the gate of theP-channel MOSFET 9a. All of the reset gates 5 in the pixels of a row andthe inter-pixel gate electrodes 5a of that row are connected in commonby reset gate interconnect 21. The P-channel MOSFETs 9 and 9a, whichserve as switching elements for the row, thus turn on and offsimultaneously in that row.

As a result, as is evident from FIG. 37, when all the MOSFETs 9 and 9afor a given row are on, all the gate areas 15 of the JFETs 2 and all thereset drains 4 of the pixels of that row are electrically connected tothe reset drain interconnect 24 for that row, and all the gate areas 15of the JFETs 2 and all the reset drains 4 for that row are electricallyconnected by the inter-pixel P-channel MOSFETs 9a. Thus, the gate areas15 of JFETs 2 of the first pixels, in which reset drain 4 is notdirectly connected to reset drain interconnect 24, are electricallyconnected to reset drain interconnect 24 for that row via the P-channelMOSFETs 9a and reset drains 4 of the fourth pixels in that row.

Conversely, when all MOSFETs 9 and 9a for a particular row are off, thegate areas 15 of the JFETs 2 for all pixels of that row are electricallydisconnected from the reset drain interconnect 24 of that row.

A vertical scan circuit applies a drive signal RSD to the gate areas 15of JFETs 2 on all the pixels in a particular row in order to move thecharge from the gate areas 15 to the reset drain interconnect 24 forthat row. The potential of the gate areas 15 may thus be controlled foreach row as a row by the vertical scan circuit. The fixed-image imagesensor array of FIG. 37 thus is operated in same way as the prior-artarray described above and shown in FIGS. 54 and 55.

In rows that include first pixels (which have the capability ofmonitoring light quantity), when all P-channel MOSFETs 9 and 9a for thatrow are on, all the gate areas 15 of JFETs 2 and all the reset drains 4for that row are electrically connected by the inter-pixel P-channelMOSFETs 9a. The reset drains 4 on the first pixels in that row are thuselectrically connected to the reset drain interconnect 24 for that rowvia the P-channel MOSFETs 9a and the reset drains 4 on said fourthpixels for that row. It is therefore possible to output, from the resetdrain interconnect 24 for a particular row, photoelectric current basedon the signal charge (in this embodiment, the hole) generated inproportion to the incident light entering the apertures 24a in the firstpixels.

As may be understood from the foregoing, in the rows that include firstpixels, reset drains 4, which constitute the photodiodes 40 on the firstpixels, are not directly connected electrically to the reset draininterconnect 24 for that row. Instead, the on/off condition of all theP-channel MOSFETs 9 and 9a for that row determine whether the resetdrains 4 on these first pixels are electrically connected or cut offfrom the reset drain interconnect 24 for that row.

This embodiment of a fixed-image image sensor array includes peripheralcircuitry comprising sort-processing circuit 27, vertical scan circuit7, and horizontal scan circuit 8. This peripheral circuitry is the sameas that of the prior-art fixed-image image sensor array, described aboveand shown in FIGS. 54 and 55, except that in this embodiment, in rowsthat include first pixels, the reset drain interconnect 24 for isconnected to an output terminal 50 via a switch QB, and to the verticalscan circuit 7 via a switch QA. A drive pulse φPD is applied to the gateelectrodes of each switch QA, and pulse resulting from the inversion, byinverter 51, of the drive pulse φPD pulse is applied to the gateelectrodes of each switch QB. The switches QA and QB thus constitute aswitching element that switches between a condition in which the chargesin the gate areas 15 in each pixel in a particular row are dischargedonto reset drain interconnect 24 and supplied with a drive signal φRSDto control the potential of the gate areas 15, and a condition in whichthe signal that emerges in the interconnect 24 is output via outputterminal 50. Consequently, this embodiment is capable of outputting atoutput terminal 50 the photoelectric current Ip generated by the resetdrains 4 of the first pixels.

Image Capture Apparatus Example Embodiment 1

FIG. 38 is a general block diagram showing an example of a fixed-imageimage capture device utilizing this embodiment of a fixed-image imagesensor array. A fixed-image image sensor array 100 is placed inside ablack box 102 equipped with a light shielding shutter 101. Controller103 controls fixed-image image sensor array 100 and shutter 101. Theoutput terminal 50, which outputs photoelectric current Ip to serve asthe light quantity monitoring signal from the fixed-image image sensorarray 100 is electrically connected to a photoelectric current processorcircuit 104. The photoelectric current processor circuit 104 includes aphotoelectric current integrator circuit 105 and a comparator 106.Photoelectric current integrator circuit 105 is comprises an operationalamplifier 107, a capacitor CL and a reset switch 108, connected as shownin the figure. The reset switch 108 discharges the charge in capacitorCL in response to reset signal φRST received at the gate electrode, thusresetting photoelectric current integrator circuit 105. Thephotoelectric current integrator circuit 105 integrates thephotoelectric current Ip from the output terminal 50 and converts itinto a voltage Vip. The comparator 19 compares this Vip with thereference voltage Vc, and when the voltage Vip is smaller than thereference voltage Vc, it outputs a control signal 109 to controller 103,which then closes shutter 101.

FIG. 39 is a timing chart for the fixed-image image sensor array 100 andthe shutter 101 useful for capturing still (fixed) images using thefixed-image image capture apparatus shown in FIG. 38.

For the first half T1a of interval T1, the transfer gates 3 are turnedon for all pixels, the charge on photodiodes 1 for all pixels istransferred to the gate areas 15 of the JFETs 2, and the photodiode 1 isthus reset. Still during T1a, the transfer gates 3 are then turned offby the return to the low level of the respective driving pulses φTG.During this time T1a, the respective driving pulses φRSD are set to thevoltage VGH. Since the driving pulses φRSG are low, the P-channelMOSFETs 9 and 9a are all on, and the gate areas 15 of the JFETs 2 areall set to the voltage VGH.

Next, during the second half T1b of interval T1, the drive pulses φRSDgo to high level, and since at this time the P-channel MOSFETs 9 and 9aall are still on, the gate areas 15 of the JFETs 2 of all pixels are setto the voltage VGL (a potential level that turns off JFETs 2). Pixelinitialization is thus complete, and exposure can begin.

During interval T2, shutter 101 opens and the apparatus goes intoexposure mode. At this time, the P-channel MOSFETs 9 and 9a for rowsthat include the first pixels (which possesses light quantity monitoringcapabilities) all go on, while pulse φPD is low level. Accordingly,switch QB turns on while switch QA is off, such that reset draininterconnect 24 is connected to output terminal 50. As a result,photoelectric current Ip generated by the first pixels, located in thecenter of the image capture surface in the fixed-image image sensorarray 100, flows to photoelectric current processing circuit 104, andthe output voltage Vip from the photoelectric current integrator circuit108 changes as shown in FIG. 39. The voltage Vip is proportional to theintensity of light incoming to fixed-image image sensor array 100, so bymonitoring voltage Vip it is possible to determine the desired exposurein real time during exposure. In other words, in FIG. 39, at the pointin time when output voltage Vip from photoelectric current integratorcircuit 108 exceeds reference voltage Vc, the control signal 109 is sentfrom the photoelectric current processor circuit 104 to the controller16, which closes the shutter 101. Thereafter, each row of thefixed-image image sensor array is read-out in sequence.

During interval T3, switch QB is off while switch QA is on, whichconnects reset drain interconnect 24 to vertical scan circuit 7. At thistime, (taking the first interval T3 as an example) the P-channel MOSFETs9 and 9a of the first (1st) row to be read-out are all on, and thedriving pulse RSD for the first row is high (at VGH). This sets the gateareas 15 of the JFETs 2 of the first row to voltage VGH. Thereafter theP-channel MOSFETs 9 and 9a of the first row go off and go into floatingmode.

During interval T4, signals are read out in source-follower mode fromthe source areas 14 of the JFETs 2 of the first row, and are stored inthe capacitors 28 in the sort-processing circuit 27 as reference signalsVref (reference or "dark" output). In addition, driving pulse φN goeslow, turning switch 29 off and putting the output sides (sides 29-1 to29-n) of capacitors 28 into floating mode.

During interval T5, driving pulse φTGi goes low and the optical signalcharges stored in photodiodes 1 are thus transferred to the gate areas15 of the JFETs 2 in the first row via the transfer gates 3. Since theoutput side of capacitor 28 is in floating mode at this time, itproduces a differential signal Vs-Vref, representing the differentialbetween the optical signal Vs (actual or "combined" output) read-outfrom JFET2 source areas 14 and reference signal Vref (reference or"dark" output).

During interval T6, the horizontal scan circuit 8 sequentially turns onthe horizontal-select switches 39-1 through 39-n, and the differentialsignals Vs-Vref for each pixel on the first row are read out fromcapacitors 28-1 to 28-n as image signals, and are output from outputterminal OUT via output amplifier 35.

The intervals T3 through T6 are repeated in sequence for all rowsthrough the last row, row m.

In this manner, fixed-image Image-sensor array 100 in this embodiment isable to monitor in real time the quantity of light directly entering thefixed-image image sensor array during an exposure. As a result, thefixed-image image capture apparatus utilizing this fixed-image imagesensor array 100 as shown in FIG. 38 is always able to capture imageswith the optimal exposure time, even when the quantity of incoming lightchanges during an exposure.

Image Capture Apparatus Example Embodiment 2

Another example usage of the fixed-image image sensor array 100 is shownin FIG. 40.

FIG. 40 is a schematic diagram showing another example of a fixed-imageimage capture apparatus utilizing the fixed-image image sensor array100. In FIG. 40, elements identical or corresponding to elements in FIG.38 are assigned the same reference characters, and the descriptionthereof will not be repeated.

The image capture apparatus of FIG. 40 has a different exposure controlsystem than the image capture apparatus of FIG. 38. In the image captureapparatus shown in FIG. 38, at the point in time when the optimalexposure quantity has been obtained, shutter 103 is closed, and theexposure time is terminated. In the image capture apparatus of FIG. 40,a supplemental light emitting apparatus (e.g., a strobe) 610 is used toilluminate the subject. At the point in time when the total exposurelight that has entered fixed image capture apparatus 100 is optimal,light emission from strobe 610 is halted. This is the exposure controlused in this example. The image capture apparatus shown in FIG. 40differs in configuration from the image capture apparatus shown in FIG.38 only in that it is equipped with a strobe 610 instead of a shutter103.

FIG. 41 is timing chart for fixed-image image sensor array 100 andstrobe 610 when the image capture apparatus shown in FIG. 40 is used tocapture still images. The timing chart shown in FIG. 41 substitutesstrobe on/off for the shutter on/off in the timing chart in FIG. 40. Allother operations are the same, and the explanation thereof is thus notrepeated.

When using a strobe, the light reflected off the subject, and,therefore, the quantity of light entering fixed image capture apparatus100, varies. Accordingly, the advantages are great from the ability ofthis embodiment to monitor the quantity of entering light in real timeduring exposure, and thereby to always capture images with the optimalexposure irrespective of the subject.

MODIFICATIONS TO THE IMAGE SENSOR ARRAY

As discussed previously, the example embodiment fixed-image image sensorarray shown in FIG. 37 consists of a two-dimensional matrix (m×n) of thefirst pixels shown in FIGS. 25 and 26(a), and the fourth pixels shown inFIGS. 27 and 28(a).

The present invention is not limited to this kind of structure. It mayalso be composed of an appropriate combination of the above-discussedfirst through fourteenth pixels, including the above-discussedmodifications of the twelfth through fourteenth pixels. At least onetype of pixel with light-quantity monitoring capability should be usedas at least one pixel among all the pixels. When all the MOSFETs 9 andMOSFETS 9a (if any) are on for a particular row in the two-dimensionalmatrix, the gate areas 15 of the JFETs 2 and the reset drains 4 of allthe pixels on that row are electrically connected to the reset draininterconnect 24 of that row. When all the MOSFETs 9 and MOSFETs 9a (ifany) for that row are off, the gate areas 15 of the JFETs 2 for all thepixels of that row are electrically disconnected from the reset draininterconnect 24 of that row. When all the P-channel MOSFETs 9 and 9a areon for a row that includes pixels with light quantity monitoringcapabilities, the reset drains 4 of the pixels with light quantitymonitoring capabilities should be electrically connected to the resetdrain interconnect 24 for that row.

For example, in the example embodiment as shown in FIG. 37, (1) any ofsaid eighth through eleventh pixels may be put in place of said firstpixel, (2) any of said fifth through seventh pixels may be substitutedfor said fourth pixels in rows that do not include said first pixels, orin rows that do include said first pixels, but not adjacent to saidfirst pixels, and (3) any of said eighth through eleventh pixels may besubstituted for pixels that are adjacent to said fourth pixels.

In addition, it is possible in the two-dimensional matrix arrangement tohave at least one out of all the pixels (and possibly all, of course) beany of said eighth through eleventh pixels, and to have the rest be anyof said fourth through seventh pixels. When any of the eighth througheleventh pixels, which possess light monitoring capabilities, is used,the reset drains 4 that constitute the photodiodes 40 are directlyelectrically connected to the reset drain interconnect 24 for that row,irrespective of the on/off status of the MOSFETs 9 and MOSFETs 9a forthat row.

Since the twelfth and fourteenth pixels correspond to the first pixel,and the thirteenth pixel corresponds to the fourth pixel, it is alsopossible to obtain further variations of the fixed-image image sensorarray by replacing first pixels with the twelfth pixels or fourteenthpixels, and by replacing fourth pixels with the thirteenth pixels. Theresulting fixed-image image sensor array performs the same functions asthat of the first example embodiment, and yields the same advantages.

In addition, the arrangement and quantity of pixels that have a lightmonitoring function may be modified. It is not necessarily required thatsaid pixels be arranged in the center nor, that they be arranged in asingle group.

Furthermore, in the example embodiment of FIG. 37, the light-quantitymonitor signals from the multiple pixels with light quantity monitoringcapabilities were consolidated into one for output from output terminal50. However, it is also possible to output the light-quantity monitorsignals separately from various pixels, as needed.

Image Sensor Array Example Embodiment 2

FIG. 42 is a circuit diagram of a second example embodiment afixed-image image sensor array. In FIG. 42, elements identical orcorresponding to elements in FIG. 37 are assigned the same referencecharacters, and the description thereof will not be repeated.

Whereas said first example embodiment is a two-dimensional fixed-imageimage sensor array, this example embodiment is a one-dimensionalfixed-image image sensor array.

This example embodiment comprises a single row of pixels including firstpixels, along with related peripheral circuitry.

This embodiment yields the same advantages as the first exampleembodiment.

Moreover, the modifications previously described for the first exampleembodiment may be applied similarly to this embodiment as well.

Microlenses Example Embodiments

The image sensor arrays of the present invention can benefit from theuse of on-chip microlenses to increase the light-sensitivity and theeffective aperture ratio of the arrays. The microlenses of the presentinvention are specially configured to cooperate with one or more pixelshaving two photosensitive elements.

Microlenses Example Embodiment 1

FIG. 43 shows an example embodiment of a microlens arrangement for usein the context of the present invention. FIG. 43(a) is a plan view andFIG. 43(b) is a cross-sectional view taken along the line A-A' in FIG.43(a).

In this example embodiment, a single pixel 702A has both a firstphotoelectric conversion element, such as a photodiode, positioned belowan aperture 701, and a second photoelectric conversion elementpositioned below an aperture 702. The second photoelectric conversionelement at aperture 702 is positioned near the center of the fixed-imageimage sensor array. The pixel 702A is surrounded by conventional singlepixels 701A without second photoelectric conversion elements. FIG. 43represents an enlargement of a single pixel 702A and the surroundingsingle pixels 701A that form a portion of a larger array of pixels.

In FIG. 43, 701 is the aperture over the first photoelectric conversionelement, and 702 is the aperture over the second photoelectricconversion element. A standard on-chip microlens 703 is used inexisting-type pixels 701A, while a reduced-size on-chip microlens 704 isused in the pixel 702A. (Hereafter, on-chip microlenses may be referredto simply as microlenses). A microlens 704 is also used in the pixel701A that is adjacent to pixel 702A on the upper side in FIG. 43(a). Inother words, the standard pixel 701A having a first photoelectricconversion element nearest the aperture 702 is not equipped with astandard microlens 703. Equipping it with a standard microlens 703 wouldcover up the aperture 702 over the second photoelectric conversionelement.

In this embodiment, the separation between neighboring microlenses 703is, for example, on the order of 0.2 microns horizontally andvertically. The horizontal separation between microlenses 704 is thenlikewise about 0.2 microns horizontally, but the vertical separation isenlarged so as to avoid the aperture 702 in the second photoelectricconversion element. The microlenses 704 are reduced and shaped in orderto focus light on the first photoelectric conversion elements.

Both microlenses 703 and 704 use dome-shaped lenses (toric surface) inorder to increase the covered area as much as possible to achieve thehighest effective pixel aperture ratio. They are arranged so that thecenter point of the first photoelectric conversion element is alignedwith the center point of the microlens.

In this example embodiment, microlenses 704 that focus light on thefirst photoelectric conversion element are placed so as to avoidaperture 702 on the second photoelectric conversion element. Thus, lightentering the second photoelectric conversion element is not blocked orrefracted by the microlenses focusing light on the first photoelectricconversion elements. Pixels 701A that are not adjacent to pixel 702A usea large standard microlens 703.

The example microlens embodiment of FIG. 43 makes it possible toefficiently illuminate the aperture 702 over the second photoelectricconversion element without degrading the effective aperture ratio of thegreat majority of the pixels. This example embodiment also makes itpossible to increase the effective aperture ratio of the fixed-imageimage sensor array while still monitoring the quantity of incident lightduring exposure.

The on-chip microlens used in this invention may be either a hemisphericlens, or a cylindrical lens extending along the row of pixels as shownin FIG. 45.

In FIG. 43 the microlenses adjacent to the second photoelectricconversion element have a different size than other microlenses.However, if desired, the same size may be used for all microlenses.

Microlenses Example Embodiment 2

FIG. 44 shows a second example embodiment of microlenses useful in thecontext of the present invention. FIG. 44(a) is a plan view, and FIG.44(b) is a cross-sectional view taken along the line A-A' in FIG. 44(a).

Except for the microlenses themselves, this embodiment has the samestructure as Embodiment 1 shown in FIG. 43. In FIG. 44, a hole 706 isformed by cutaway areas in microlenses 707 and 708. An Al film 709 ispositioned on the side walls of the hole 706.

To produce the structure of this example embodiment, microlenses 703that are the same as microlenses 703 in Embodiment 1 of FIG. 43 areplaced over the entire surface with a horizontal and vertical separationof, for example, 0.2 microns. In addition, said microlenses 703 usedome-shaped lenses (toric surfaces) in order to increase the coveredarea as much as possible to achieve the highest effective pixel apertureratio. The microlenses 703 are arranged so that the center point of theeach first photoelectric conversion element is aligned with the centerpoint of a microlens.

Next, photolithography technology is used to remove only the portion ofthe microlens covering pixel(s) 702A having an aperture 702 over asecond photoelectric conversion element. This creates the hole 706 inmicrolenses above aperture 702 on the second photoelectric conversionelement. Microlenses 707 and 708 are thus formed, each of which has aportion cut away.

Then a light-shielding film 709 such as an Al (aluminum) film is placedon the side walls of hole 706, as indicated in FIG. 44. This is done toprevent cross-talk between the light entering aperture 702 on the secondphotoelectric conversion element and the light entering aperture 701 onthe first photoelectric conversion element. The light-shielding Al filmmay be formed by using Al sputtering to deposit the Al film over theentire microlens surface, including the previously formed hole 706, thenanisotropic etching such as RIE (reactive ion etching) to etch only theAl film on the bottom of hole 706 and on the tops of the microlenses,leaving light-shielding film 709 on the side walls of hole 706.

The first example embodiments described above did not employ anymicrolens in the area B of pixel 702A shown in FIG. 44. As a result,light reaching that region could not be focused on any firstphotoelectric conversion element. With this second example embodiment,however, light entering area B can be focused on the respective firstphotoelectric conversion elements, thereby increasing the effectiveaperture ratio of pixel 702A and pixel 701A adjacent pixel 702A on theupper side thereof in FIG. 44.

The on-chip microlens used in this invention may be either a hemisphericor a cylindrical lens. In this second example embodiment, hole 706 iscut only on pixels having a second photoelectric conversion element.However, a hole may be cut on all pixels, if desired. The same sizemicrolens is used for all pixels in this second sample embodiment, butas with the first example embodiment, a different microlens size may beused for microlenses adjacent to the second photoelectric conversionelement.

Microlenses Example Embodiment 3

FIG. 46 illustrates a third example embodiment of microlenses useful inthe context of the present invention. In this example embodiment, asmaller microlens 712 focuses light on the first photoelectricconversion elements surrounding the second photoelectric conversionelement, and a larger microlens 713 focuses light on the secondphotoelectric conversion element. Except for the microlenses, thisembodiment has the same structure as the first sample embodiment, shownin FIG. 43.

In this third example embodiment, the microlens 713 is formed directlyabove the aperture 702 over the second photoelectric conversion elementso as to focus light on the second photoelectric conversion element. Asmaller microlens 712 is formed, for pixel 702A and the three pixels701A around pixel 702A, at a distance of, for example, 0.2 microns frommicrolens 713, so as to focus light on the first photoelectricconversion element. Standard microlenses 703 are formed to focus lighton the first photoelectric conversion elements not next to aperture 702.

The center point of microlenses 703, 712, and 713 are aligned with thecenter points, respectively, of the first and second photoelectricconversion elements, which is the area where they are focusing light.The vertical separation between microlens 712 and microlens 703 isincreased. The lenses used for these microlenses are dome-shaped lenses(toric lens surfaces).

In this embodiment, since microlens 713 is also placed above the secondphotoelectric conversion element, it is possible to increase theeffective aperture ratio of the second photoelectric conversion element.Therefore, it is possible to monitor the quantity of incoming lightduring exposure, even when only a very small amount of light isavailable. This makes more highly sensitive TTL (through-the-lens) lightmodulation/metering possible.

Example Embodiment of Image Capture Circuity and Processing

FIG. 47 is a block diagram of the overall configuration of an imagecapture circuitry and processing useful with certain of the microlensarrangements of the present invention. The image capture apparatus ofFIG. 47 comprises an image read-out control MPU (microprocessor unit)2200, a timing generator 2201, an image output signal read driver 2202,a fixed-image image sensor array 2203, an image output signal amplifier2204, an A/D converter 2205, an aperture ratio adjustment processor2206, a signal processor 2207 for performing signal correction, a memorycontroller 2208, an image output device interface 2209, and a CRT orother image output device 2210.

Entering light is converted by the fixed-image image sensor array 2203into an electrical signal, and after it is amplified by amplifier 2204,it is converted into a digital signal by A/D converter 2205. Theeffective aperture ratio is adjusted as needed by aperture ratioadjustment processor 2206, after which the signal is sent to signalprocessor 2207. The signal processing in signal processor 2207 isperformed in conventional fashion, with the appropriately selectedprocessing performed as needed. After undergoing signal processing, thesignal enters memory controller 2208 and is stored in image memory,after which it is sent via interface 2209 to image output device 2210.

FIG. 48 is a flowchart showing the operations of the image captureapparatus of FIG. 47.

When light enters the image capture element (S1), MPU 2200 determineswhether the microlens on the first photoelectric conversion element(image capture element) on the pixel that has received the light is astandard microlens or not (S2). A standard microlens is a microlens suchas the microlenses 703 shown in FIGS. 43 and 44. Non-standardmicrolenses are those such as microlenses 704 in FIG. 43 or microlenses707 and 708 in FIG. 44, i.e., small or specially shaped microlenses suchas used in pixel(s) 702A and in pixel(s) 701A which are adjacent topixel(s) 702A.

If the microlens is a standard one, conventional signal processingproceeds (S3a). If the microlens is non-standard, aperture ratioadjustment is performed (S3b), after which conventional signalprocessing proceeds (S3a). Then image output is performed (S4). When thestandard microlens effective aperture ratio is 90% and the non-standardmicrolens effective aperture ratio is 60%, the aperture ratio adjustmentmethod is to multiply the output signal from an image capture elementwith a non-standard microlens by 1.5 (=90/60) before output.

Performing this aperture adjustment processing makes it possible tooutput images with no variation in sensitivity between pixels.

While the invention has been described above by way of exemplaryembodiments, it is understood that many changes and substitutions may bemade by those skilled in the art with without departing from the spiritand the scope of the invention, which is not limited to the aboveembodiments, but is defined instead by the literal and equivalence scopeof the appended claims.

What is claimed is:
 1. A photoelectric conversion device comprising:(a)a photoelectric conversion element structured and arranged so as togenerate, in response to incident light, a first signal chargecorresponding to the incident light; (b) an output unit comprising anamplification transistor having a control electrode, the amplificationtransistor being structured and arranged such that the control electrodegenerates, in response to the incident light, a second signal chargecorresponding to the incident light, and the output unit beingstructured and arranged so as to output an electric signal correspondingto a charge present in the control electrode; and (c) a transfer unitstructured and arranged so as to transfer to the control electrode thefirst signal charge generated by the photoelectric conversion element,the transfer unit being supplied with a control signal so as to transferthe first signal charge in a manner either (1) so as to cause the outputunit to output an electric signal corresponding to the sum of the firstand second signal charges or (2) so as to cause the output unit toseparately output both an electric signal corresponding to the firstsignal charge and an electric signal corresponding to the second signalcharge.
 2. The photoelectric conversion device of claim 1, wherein theamplification transistor is a field-effect transistor.
 3. Thephotoelectric conversion device of claim 1, wherein a color filter of aspecific color is provided above at least one of (1) anincident-light-receiving surface of the control electrode of theamplification transistor and (2) an incident-light-receiving surface ofthe photoelectric conversion element.
 4. The photoelectric conversiondevice of claim 1, wherein a color filter of a specific color isprovided above are incident-light-receiving surface of the controlelectrode of the amplification transistor and a color filter of adifferent color is provided above an incident-light-receiving surface ofthe photoelectric conversion element.
 5. A photoelectric conversionapparatus comprising:the photoelectric conversion device of claim 1; ashutter; and a controller structured and arranged so as to control thetiming of the shutter so as to adjust the time during which thephotoelectric conversion element generates a charge based on the secondsignal charge generated by the control electrode of the amplificationtransistor.
 6. A photoelectric conversion apparatus comprising:thephotoelectric conversion device of claim 1; a shutter; and a controllerstructured and arranged to as to control the timing of the shutter basedon the sum of (1) the signal charge generated by the control electrodeof the amplification transistor and (2) the signal charge generated bythe photoelectric conversion element, thereby adjusting the time duringwhich the photoelectric conversion element generates a charge.
 7. Aphotoelectric conversion device comprising:(a) a photoelectricconversion element structured and arranged so as to generate, inresponse to incident light, a first signal charge corresponding to theincident light; (b) an output unit comprising an amplificationtransistor having a control electrode, the output unit structured andarranged so as to output an electric signal corresponding to a chargepresent in the control electrode; (c) a transfer unit structured andarranged so as to be able to transfer the first signal charge generatedby the photoelectric conversion element to the control electrode; and(d) a reset transistor positioned and arranged so as to be able toremove the charge present in the control electrode and so that at leasta main electrode of the reset transistor generates, in response to theincident light, a second signal charge corresponding to the incidentlight, the reset transistor and the transfer unit being supplied withcontrol signals so as to transfer the first signal charge to the outputunit, causing the output unit to output an electric signal correspondingto the first signal charge, and so as to cause the second signal chargeto be output from the reset transistor.
 8. The photoelectric conversiondevice of claim 7, wherein said main electrode of the reset transistoris connected to a first transistor for outputting the signal chargegenerated by said main electrode and to a second transistor for applyinga prescribed voltage to said main electrode.
 9. The photoelectricconversion device of claim 7, wherein the amplification transistor is afield-effect transistor, and the reset transistor is a MOS transistor.10. The photoelectric conversion device of claim 7, wherein a colorfilter of a specific color is positioned above at least one of (1) anincident-light-receiving surface of said main electrode of the resettransistor and (2) an incident-light-receiving surface of thephotoelectric conversion element.
 11. The photoelectric conversiondevice of claim 7, wherein a color filter of a specific color isprovided above an incident-light-receiving surface of said mainelectrode of the reset transistor and a color filter of a differentcolor is provided above an incident-light-receiving surface of thephotoelectric conversion element.
 12. A photoelectric conversionapparatus comprising:the photoelectric conversion device of claim 7; ashutter; and a controller structured and arranged so as to control thetiming of the shutter based on the second signal charge generated saidmain electrode of the reset transistor, thereby adjusting the timeduring which the photoelectric conversion element generates a charge.13. A photoelectric conversion device comprising:(a) a photoelectricconversion element structured and arranged so as to generate, inresponse to incident light, a first signal charge corresponding to theincident light; (b) an output unit comprising an amplificationtransistor having a control electrode, the output unit being structuredand arranged so as to output an electric signal corresponding to acharge present at the control electrode; (c) a transfer unit positionedand arranged so as to be able to transfer the first signal chargegenerated by the photoelectric conversion element to the controlelectrode; and (d) a reset transistor structured and arranged so as tobe able to remove from the control electrode the charge present at thecontrol electrode, the reset transistor being further structured andarranged so that at least a main electrode thereof generates, inresponse to the incident light, a second signal charge corresponding tothe incident light, the reset transistor and the transfer unit beingsupplied with control signals so as to transfer the first and secondsignal charges to the control electrode either (1) such that the firstand second signal charges are combined at the control electrode, or (2)such that the first and second signal charges are successively andindividually present in the control electrode.
 14. The photoelectricconversion device of claim 13, wherein the amplification transistor is afield-effect transistor, and the reset transistor is a MOS transistor.15. The photoelectric conversion device of claim 13, wherein a colorfilter of a specific color is positioned above at least one of (1) anincident-light-receiving surface of said main electrode of the resettransistor and (2) an incident-light-receiving surface of thephotoelectric conversion element.
 16. The photoelectric conversiondevice of claim 13, wherein a color filter of a specific color isprovided above an incident-light-receiving surface of said mainelectrode of the reset transistor, and a color filter of a differentcolor is provided above an incident-light-receiving surface of thephotoelectric conversion element.
 17. A photoelectric conversionapparatus comprising:the photoelectric conversion device of claim 13; ashutter; and a controller structured and arranged so as to control thetiming of the shutter based on the second signal charge generated saidmain electrode of the reset transistor, thereby adjusting the timeduring which the photoelectric conversion element generates a charge.18. A photoelectric conversion device comprising:(a) a photoelectricconversion element structured and arranged so as to generate, inresponse to incident light, a first signal charge corresponding to theincident light; (b) an output unit comprising an amplificationtransistor having a control electrode, the output unit being structuredand arranged so as to output an electric signal corresponding to acharge present at the control electrode, the amplification transistorbeing structured and arranged such that the control electrode generates,in response to the incident light, a second signal charge correspondingto the incident light; (c) a transfer unit structured and arranged so asto be able to transfer the first signal charge generated by thephotoelectric conversion element to the control electrode; and (d) areset transistor structured and arranged so as to be able to remove fromthe control electrode the signal charge present at the controlelectrode, the reset transistor being further structured and arranged sothat at least a main electrode thereof generates, in response to theincident light, a third signal charge corresponding to the incidentlight, the reset transistor and the transfer unit being supplied withcontrol signals so as to transfer the first signal charge to the controlelectrode and so as to transfer the second and third signal charges tosaid main electrode of the reset transistor for output from said mainelectrode, the second and third signal charges being either (1) combinedat said main electrode and output together as a combined signal charge,or (2) output sequentially at said main electrode.
 19. The photoelectricconversion device of claim 18, wherein said main electrode of the resettransistor is connected to both a first transistor for outputting thesecond and third signal charges, and to a second transistor for applyinga prescribed voltage to said main electrode.
 20. The photoelectricconversion device of claim 18, wherein the amplification transistor is afield-effect transistor, and the reset transistor is a MOS transistor.21. The photoelectric conversion device of claim 18, wherein a colorfilter of a specific color is provided above at least oneincident-light-receiving surface from among (1) anincident-light-receiving surface of the control electrode of theamplification transistor, (2) an incident-light-receiving surface ofsaid main electrode of the reset transistor, and (3) anincident-light-receiving surface of the photoelectric conversionelement.
 22. The photoelectric conversion device of claim 18, wherein acolor filter of a specific color is provided above anincident-light-receiving surface of the photoelectric conversion elementand a color filter of a different color is provided above at least oneof (1) an incident-light-receiving surface of the control electrode ofthe amplification transistor and (2) an incident-light-receiving surfaceof said main electrode of the reset transistor.
 23. A photoelectricconversion apparatus comprising:the photoelectric conversion device ofclaim 18; a shutter; and a controller for controlling the timing of theshutter based on at least one of (1) the signal charge generated by thecontrol electrode of the amplification transistor, and (2) the signalcharge generated by said main electrode of the reset transistor, therebyadjusting the time during which the photoelectric conversion elementgenerates a charge.
 24. The photoelectric conversion apparatus of claim23, wherein the controller closes the shutter when an electric signaloutput from the output unit exceeds a first prescribed value, or when asignal charge output from said main electrode of the reset transistorexceeds a second prescribed value, whichever comes first, therebyadjusting the time during which the photoelectric conversion elementgenerates a charge.
 25. A photoelectric conversion device comprising:(a)a photoelectric conversion element structured and arranged so as togenerate, in response to incident light, a first signal chargecorresponding to the incident light; (b) an output unit comprising anamplification transistor having a control electrode, the output unitbeing structured and arranged so as to output an electric signalcorresponding to a charge present at the control electrode, theamplification transistor being structured and arranged such that thecontrol electrode generates, in response to the incident light, a secondsignal charge corresponding to the incident light; (c) a transfer unitstructured and arranged so as to be able to transfer to the controlelectrode the first signal charge generated by the photoelectricconversion element; and (d) a reset transistor structured and arrangedso as to be able to remove from the control electrode the charge presentat the control electrode, the reset transistor being further structuredand arranged such that at least a main electrode thereof generates, inresponse to the incident light, a third signal charge corresponding tothe incident light, the reset transistor and the transfer unit beingsupplied with control signals so as to output the third signal chargefrom said main electrode of the reset transistor and so as to transferto the control electrode both the first and second signal charges, thefirst and second signal charges being so transferred either (1) so as tocombine the first and second signal charges at the control electrode, or(2) so as to make the first and second signal charges individuallypresent at the control electrode in succession.
 26. The photoelectricconversion device of claim 25, wherein said main electrode of the resettransistor is connected to both a first transistor for outputting thethird signal charge, and to a second transistor for applying aprescribed voltage to said main electrode.
 27. The photoelectricconversion device of claim 25, wherein the amplification transistor is afield-effect transistor, and the reset transistor is a MOS transistor.28. The photoelectric conversion device of claim 25, wherein a colorfilter of a specific color is provided above at least oneincident-light-receiving surface from among (1) anincident-light-receiving surface of the control electrode of theamplification transistor, (2) an incident-light-receiving surface ofsaid main electrode of the reset transistor, and (3) anincident-light-receiving surface of the photoelectric conversionelement.
 29. The photoelectric conversion device of claim 25, wherein acolor filter of a specific color is provided above anincident-light-receiving surface of the photoelectric conversion elementand a color filter of a different color is provided above at least oneof (1) an incident-light-receiving surface of the control electrode ofthe amplification transistor and (2) an incident-light-receiving surfaceof said main electrode of the reset transistor.
 30. A photoelectricconversion apparatus comprising:the photoelectric conversion device ofclaim 25; a shutter; and a controller for controlling the timing of theshutter based on at least one of (1) the signal charge generated by thecontrol electrode of the amplification transistor, and (2) the signalcharge generated by said main electrode of the reset transistor, therebyadjusting the time during which the photoelectric conversion elementgenerates a charge.
 31. The photoelectric conversion apparatus of claim30, wherein the controller closes the shutter when an electric signaloutput from the output unit exceeds a first prescribed value, or when asignal charge output from said main electrode of the reset transistorexceeds a second prescribed value, whichever comes first, therebyadjusting the time during which the photoelectric conversion elementgenerates a charge.
 32. A photoelectric conversion device comprising:(a)a photoelectric conversion element structured and arranged so as togenerate, in response to incident light, a first signal chargecorresponding to the incident light; (b) an output unit comprising anamplification transistor having a control electrode, the output unitbeing structured and arranged to as to output an electric signalcorresponding to a charge present at the control electrode, theamplification transistor being structured and arranged such that thecontrol electrode generates, in response to the incident light, a secondsignal charge corresponding to the incident light; (c) a transfer unitstructured and arranged so as to be able to transfer the first signalcharge generated by the photoelectric conversion element to the controlelectrode; and (d) a reset transistor structured and arranged so as tobe able to remove from the control electrode the charge present at thecontrol electrode, the reset transistor being further structured andarranged such that at least a main electrode thereof generates, inresponse to the incident light, a third signal charge corresponding tothe incident light, the reset transistor and the transfer unit beingsupplied with control signals so as to cause the first, second, andthird signal charges to be present, at the control electrode of theamplification transistor, with (1) all three signal charges combined atonce at the control electrode, (2) all three signal charges individuallyin succession present at the control electrode, or (3) the first signalcharge present individually and the second and third charges present incombination at the control electrode.
 33. The photoelectric conversiondevice of claim 32, wherein the amplification transistor is afield-effect transistor, and the reset transistor is a MOS transistor.34. The photoelectric conversion device of claim 32, wherein a colorfilter of a specific color is provided above at least oneincident-light-receiving surface from among (1) anincident-light-receiving surface of the control electrode of theamplification transistor, (2) an incident-light-receiving surface ofsaid main electrode of the reset transistor, and (3) anincident-light-receiving surface of the photoelectric conversionelement.
 35. The photoelectric conversion device of claim 32, wherein acolor filter of a specific color is provided above anincident-light-receiving surface of the photoelectric conversion elementand a color filter of a different color is provided above at least oneof (1) an incident-light-receiving surface of the control electrode ofthe amplification transistor and (2) an incident-light-receiving surfaceof said main electrode of the reset transistor.
 36. A photoelectricconversion apparatus comprising:the photoelectric conversion device ofclaim 32; a shutter; and a controller for controlling the timing of theshutter based on at least one of (1) the signal charge generated by thecontrol electrode of the amplification transistor, and (2) the signalcharge generated by said main electrode of the reset transistor, therebyadjusting the time during which the photoelectric conversion elementgenerates a charge.
 37. The photoelectric conversion apparatus of claim36, wherein the controller closes the shutter when an electric signaloutput from the output unit exceeds a first prescribed value, or when asignal charge output from said main electrode of the reset transistorexceeds a second prescribed value, whichever comes first, therebyadjusting the time during which the photoelectric conversion elementgenerates a charge.
 38. A light receiving device useful as a pixelelement in a photodetector array, the device comprising:(a) aphotosensitive element structured and arranged so as to generate, inresponse light incident thereon, a first signal charge; and (b) a firsttransistor having at least one electrode structured and arranged so asto generate, in response to light incident on said electrode, a secondsignal charge; the first transistor being positioned and arranged withinthe device in one of the two following ways:(i) the first transistorbeing positioned and arranged within the device to function as anamplification transistor, the said electrode comprising a gate of thefirst transistor connected to the photosensitive element in such a wayas to be capable of receiving the first signal charge; and (ii) thefirst transistor being positioned and arranged within the device tofunction as a reset transistor, connected to the photosensitive elementin such a way as to be able to remove the first signal charge from thedevice, the said electrode comprising a reset drain of the resettransistor,wherein the photosensitive element and the first transistorare positioned together within the device so as to facilitate formationof an extended array of such devices.
 39. An photosensitive arraycomprising multiple instances of the device of claim
 38. 40. An imagesensor array comprising a regular array of pixel elements formed on asingle semiconductor substrate, the array of pixel elements including atleast one first pixel element, said at least one first pixel elementcomprising at least first and second photosensitive areas, said at leastfirst and second photosensitive areas of said at least one first pixelelement each being capable of providing an output signal in response toincident light, the value of any one said output signal beingindependent of any other said output signal.
 41. The image sensor arrayof claim 40 wherein the array of pixel elements is a rectangular array.42. The image sensor array of claim 41 wherein the array of pixelelements is a one-dimensional array.
 43. The image sensor array of claim41 wherein the array of pixel elements is a two-dimensional array. 44.The image sensor array of claim 40 wherein the array further includes atleast one second pixel element, said at least one second pixel elementincluding one and only one photosensitive area.
 45. The image sensorarray of claim 44 wherein each pixel includes an amplifier and theoutput signal from the first photosensitive area is read out via theamplifier.
 46. The image sensor array of claim 45 wherein the outputsignal from the second photosensitive area is read out via saidamplifier.
 47. The image sensor array of claim 45 wherein the amplifieris a junction-field-effect transistor.
 48. The image sensor array ofclaim 45 further including a reset interconnection and wherein thesecond photosensitive area is read out via the reset interconnection.49. The image sensor array of claim 48 wherein the second photosensitivearea comprises at least a portion of a reset drain.
 50. The image sensorarray of claim 48 wherein the second photosensitive area is permanentlyelectrically connected to said reset interconnection.
 51. The imagesensor array of claim 48 wherein the second photosensitive area iscapable of being intermittently electrically connected to said resetinterconnection.
 52. The image sensor array of claim 51 furthercomprising inter-pixel switches capable of electrically connecting asecond photosensitive area of one pixel with an area of another pixel,and wherein the second photosensitive area is intermittentlyelectrically connected to said reset interconnection via a pixel otherthan said at least one first pixel.
 53. The image sensor array of claim48 further comprising a switch arranged so as to be able to changebetween a first state in which a driving pulse is supplied to the resetinterconnection and a second state in which an output signal may be readfrom the reset interconnection.
 54. The image sensor array of claim 44wherein each first pixel of the array is associated with a first on-chipmicrolens so arranged as to focus incident light on the firstphotosensitive area of said first pixel, and each second pixel of thearray is associated with the first or a second on-chip microlens soarranged as to focus incident light on the one and only onephotosensitive area of said second pixel, the first microlens pixelbeing shaped and positioned with respect to said first pixel in afashion identical to how the first or the second microlens is shaped andpositioned with respect to said second pixel, the first microlens notextending above the second photosensitive area.
 55. The image sensorarray of claim 54 wherein the first microlens is cylindrical.
 56. Theimage sensor array of claim 54 wherein the first microlens issemispherical.
 57. The image sensor array of claim 44 further comprisingan on-chip microlens over the first photosensitive area and no microlensover the second photosensitive area.
 58. The image sensor array of claim57 wherein the second pixel is not adjacent to the first pixel andfurther comprising an on-chip microlens substantially the same size asthe second pixel positioned over the one and only one photosensitivearea.
 59. The image sensor array of claim 44 further comprising on-chipmicrolenses over each of the first and second pixels, said on-chipmicrolenses being virtually identical except for a hole over the secondphotosensitive area of the first pixel.
 60. The image sensor array ofclaim 59 wherein the hole has sidewalls having a reflective layerthereon.
 61. The image sensor array of claim 44 further comprising afirst on-chip microlenses over each at least one first pixel, saidon-chip microlens having a hole over the second photosensitive area ofthe first pixel, the second pixel having a second on-chip microlensvirtually identical to the first microlens.
 62. The image sensor arrayof claim 44 wherein the first photosensitive area is associated with afirst on-chip microlens positioned to focus light thereon, and thesecond photosensitive area is associated with a second on-chip microlenspositioned to focus light thereon.
 63. The image sensor array of claim44 including an aperture ratio compensator capable of adjusting theoutput signals from the first photosensitive area and the one and onlyone photosensitive area as needed so as to cancel differences in saidoutput signals attributable to a difference between an effectiveaperture ratio of the first photosensitive area and an effectiveaperture ratio of the one and only one photosensitive area.
 64. Theimage sensor array of claim 63 wherein the pixels of the array areprovided with on-chip microlenses.
 65. A fixed-image image captureapparatus comprising an (1) image sensor array for capturing an imageformed, for an exposure time, on the image sensor array, and (2) alight-control device; the image sensor array comprising a regular arrayof pixel elements formed on a single semiconductor substrate, the arrayincluding at least one photosensitive area arranged to be capable ofproviding an output signal, during an exposure time, indicative of theincident light flux at said photosensitive area during the exposuretime, the light-control device arranged to be able to control theduration of the exposure time based on the output signal from the atleast one photosensitive area.
 66. The fixed-image image captureapparatus of claim 65 further comprising a shutter for starting andending the exposure time by opening and closing, respectively, andwherein the exposure control device is arranged to be capable ofcontrolling the exposure time by controlling the shutter.
 67. Thefixed-image image capture apparatus of claim 65 further comprising astrobe for starting and ending the exposure time by turning on andturning off, respectively, and wherein the exposure control device isarranged to be capable of controlling the exposure time by controllingthe strobe.
 68. A photoelectric conversion device comprising aphotoelectric conversion element structured and arranged so as to beable to generate a signal charge in response to incident light, anamplification transistor for amplifying the signal charge from thephotoelectric conversion element; and a reset transistor for resettingthe photoelectric conversion device, wherein at least one of(1) acontrol electrode of the output amplification transistor and (2) a mainelectrode of the reset transistor is structured and arranged so as to beable to generate a signal charge in response to incident light.